The Cryogenic Process for Etching Micro-Mechanical Systems (MEMS) - Principles, Advances and Applications by Oxford Instruments Plasma Technology

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Achieving Deep Etches in the Fabrication of MEMS

The two technologies used to achieve deep etches in the fabrication of micro-electro-mechanical systems (MEMS) are the Bosch process and the Cryogenic Process. Both system and process development over the years have allowed the techniques to advance but the fundamental aspects of each remain the same. In the same timescale we have seen the increasing importance of nanoscale etching for Nano Imprint Lithography, Storage Media etc. Where MEMS structures range in depth from around 10µm up to 500µm with typical openings of >1µm. Although definitions vary nanoscale usually refers to structures below 100nm etched up to several microns deep.

Principle of The Cyrogenic Process

The Cryogenic Process also uses SF₆ to provide fluorine radicals for silicon etching. The silicon is removed in the form of SiF₄, which is volatile. The main difference is in the mechanism of sidewall passivation and mask protection. Rather than using a fluorocarbon polymer, this process relies on forming a blocking layer of oxide/fluoride (SiO_xF_y) on the sidewalls (around 10-20nm thick), together with cryogenic temperatures inhibiting attack on this layer by the fluorine radicals. The low temperature operation also assists in reducing the etch rate of the mask material, which is normally either photoresist or silicon dioxide. The attack on these materials by free radical fluorine is chemical in nature and is sensitive to temperature, with the etch rate dropping rapidly at cryogenic temperatures. The low temperature can have a bad effect on some organic materials, causing cracking. This is more severe for thicker photoresists than for thin layers. As a rough guideline, layers of resist used for this process should not be more than 1.5µm thick, to avoid the hazard of cracking. If a thicker layer is needed to achieve a very deep etch, then silicon dioxide should be used as the masking material, as this has no such cracking problems.

This can be achieved in an RIE chamber, but there are significant advantages in using a high-density plasma technique such as ICP. ICP allows a high density of free radicals to be produced without also generating a large number of highly energetic ionic species. Ionic bombardment is necessary at low levels in this process, but too much ion bombardment will cause poor profiles and a reduction in selectivity to mask material.

Pressure Used During The Cyrogenic Process

The Cryogenic Process pressure is typically kept around 10mTorr. At this level, the mean free path of the ions is much longer than the sheath width and there will be little deviation from vertical in the average ion direction. Higher pressures will have a much more severe effect on the profile than is the case for the Bosch process.

Electrode Temperature Used During The Cyrogenic Process

The temperature of the electrode should not be reduced below –130°C, as this will result in condensation of SF₆ on the wafer. This results in crystallographic oriented etching of silicon. This can affect the profile at the bottom of holes, and can change circular vias into square holes. Fine control of the electrode temperature can be used to make small adjustments to the profile of a structure, but larger adjustments should be made by adjusting the oxygen content of the process.

Variations in Etched Surfaces

Another feature often seen in deep etches is a variation in the etched surface at corners. An undercut is often seen for convex corners, while concave corners produce a more positive profile. This is related to the geometry of the process, with convex corners being open to ions approaching from a wider range of angles than is true for a feature side, while concave corners are exposed to ions approaching in fewer directions.

Ion Density and Energy and Mask Erosion

The ion energy (controlled primarily by the r.f. applied to the substrate stage) and ion density (controlled by the power applied to the ICP coil) are the primary factors affecting mask erosion. Measured DC bias values of less than 20 volts can give selectivity between silicon and oxide masks of over 750:1.

Baking the Photoresist

Photoresist should be baked after developing at 150°C for 40 minutes in a convection oven to create a fully stable structure, with minimal remaining solvents. This reduces the risk of cracking and helps achieve high selectivity.

This process is inherently clean, as there is no polymer to deposit on chamber surfaces. If the ICP is not run at too high a level, there should be only minimal deposits of sulphur in the pumping lines. Any sulphur that is released is likely to react with the oxygen and will be removed as SO₂. This means that a chamber run exclusively for this process is not going to need cleaning. The chamber should be inspected on a regular basis, and ‘o’ rings replaced periodically.

Equipment Used for The Cyrogenic Process

Cryogenic Process can be done in the same equipment as the Bosch process. It does have certain different hardware needs, but there are no incompatible requirements. These are the particular options needed to best run the cryogenic deep silicon etch process.

• Cryogenically Cooled Stage
• Low Flow Mass Flow Controller (MFC) for Oxygen
• Efficient Wafer Clamping
• Mag-Lev Turbos and Fast Response Mass Flow Controllers
• Minimum Variation in Feature Dimensions

Cryogenically Cooled Stages

This needs liquid nitrogen cooling to achieve temperatures down to –110°C. The stage should have helium injected behind the wafer to provide good thermal contact. There should not be any seals on or in the stage, as any seal material will loose its flexibility at cryogenic temperatures. This applies to both ‘o’ ring seals and lip seals. The best way to achieve a good, uniform temperature on larger wafers is to have multiple helium injection points on the stage. The temperature control on the wafer is critical, as variation in temperature will cause variation in profile.

Low Flow Mass Flow Controllers (MFC) for Oxygen

The addition of small amounts of oxygen to the SF₆ can have dramatic effects on the etch profile. This is so sensitive, that oxygen being released from the ICP tube must be taken into account. The shape of etch profile becomes more positive as more oxygen is added. Too much oxygen will cause the formation of black silicon as small imperfections in the etching surface start to act as micromasks. Applications such as moulding require very accurate control of the oxygen flow to achieve positive profiles without causing black silicon.

Efficient Wafer Clamping

Again, this is necessary in order to achieve accurate temperature control of the wafer surface. Poor clamping efficiency can result in uneven helium distribution under the wafer. Silicon has good thermal conductivity at room temperature, but is not so good at cryogenic temperatures. Small variations in the heat path under the wafer can cause large differentials in surface temperatures.

Mag-Lev Turbos and Fast Response Mass Flow Controllers

Large mag-lev turbos are not needed for this process, nor are fast response mass flow controllers, unlike the Bosch process.

Minimum Variation in Feature Dimensions

This is not a machine variable, but is important in setting up processes. Different sizes of features will show different etch characteristics (including etch depth) for a given process/time. It makes process optimisation much simpler if there is one size feature, which must be right, rather than trying to achieve a reasonable result on a range of feature sizes.

Applications of The Cyrogenic Process in Deep Etching

The basic deep processes for the Cryo process has not changed over the years the etch rates depending on the aspect ratio are typically greater then 2µm/min a couple of examples below of trench etching carried out >3µm/min see figure 1 and 2.

Figure 1

Figure 2

The aspect of the cryo etch is the very smooth sidewalls which can’t be achieved by the Bosch process, also what should be noted is this process can give positive profile, which the Bosch Process can’t do, an example is shown in Figure 3.

Figure 3

A recent advance in Cryo etching has been the elimination of the notch at the mask/Si interface which is a known issue with the process. This has been eliminated by the use of both hardware and ramping of gas ratios during the initial stages of the process, the results are shown in figures 4 and 5.

Figure 4 Notch at mask/Si interface

Figure 5 elimination of notch

A typical application of the Cryo deep process is highlighted below, the smooth sidewalls make it very applicable for moulds, optical devices etc.

MEMS

Optical Waveguides

Applications of The Cyrogenic Process in Nanoscale Etching

Cryo etching normally operates at a lower bias level (typically 15-20 volts) than the Bosch process (around 50 volts). This results in less attack on the mask material giving higher selectivity. This has been found to be extremely beneficial when etching Nanoscale structures as these usually employ novel resist types such as ZEP520, PMMA etc., which are sensitive to higher bias plasma conditions. Nanoscale etches also require smooth sidewalls the downside of the traditional Bosch etch is that since etching and passivation steps are discrete, the sidewalls will develop scalloping or a bit of isotropic etching.

We will compare cryo etching here with a couple of other techniques used for nanoscale etching. Photonic crystals require controlled etching of the silicon with smooth sidewalls figure 6 shows a typical mask with 200nm openings, figure 7 shows the result of the etch under cryo conditions to a depth of >1.6µm at an etch rate of 0.5µm/min.

Figure 6. mask pre-etch

Figure 7. Photonic crystal post etch

Figures 8 and 9 show further applications of the cryo process to nanoscale etching, in Fig. 8 we have 50nm lines and spaces etched over 500nm deep with the mask still intact, in Figure 9 we have 300nm trenches etched 15µm deep into silicon which is an aspect ratio of 50:1.

Figure 8. 50nm features etched >500nm deep

Figure 9. 300nm features etched >15µm deep (AR 50:1)

Other process techniques that can be used for nanoscale etching are gas mixing, which uses SF₆ mixed in the same step with C₄F₈, this is sometimes called Pseudo Bosch process and HBr based process chemistry.

The mixed chemistry gives reasonable etch rates, but selectivity to the mask tend to be low and it has a tendency to produce positive profiles. These can be controlled to some extent by changing the gas ratios but it is not as controllable as with the cryo process, an example is shown in Figure 10.

Figure 10. Mixed SF₆/C₄F₈

HBr process chemistry is very selective to silicon dioxide, but etch rates are slower then the cryo and the gas chemistry is not as clean as the other nanoscale techniques leading to greater chamber cleans, an example of a HBR etch stopping on a 3nm SOI layer is shown in Figure 11.

Figure 11. HBr etch Courtesy of AMO Aachen

Summary

The Bosch process offers higher etch rates but at the cost of sidewall roughness. To limit this roughness the rates are usually in the region of 10-20µm, which is still higher then the cryo process. To achieve the ultra high etch rates claimed for the Bosch process means very high flows of gas and requires very big turbomolecular pumps, which result in a higher cost of ownership. The Bosch process also does not offer very good positive profiles, which the Cryo can. The cryo process has also found a growing market in the etching of Nanostructures as the Bosch process leaves scallops in the walls, which in most case is undesirable for the application.

Both the Bosch process and Cryo process will find use in the growing field of integrated sensors and actuators, but Cryo has distinct advantages in the nanoscale arena. In the end, the user must decide which process will be most appropriate for their application.

Source: "Comparison of etch processes for patterning high aspect ratio and nanoscale features in silicon" by Oxford Instruments Plasma Technology.

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