Nanoscale Etching Using ICP Systems

By AZoNano

Table of Contents

Application of Nanotechnology
ICP Tools
Advantages of the Cobra Source
Difficulties and Limits of Nanoscale Etching
Nanoscale Etching by ICP
Nano-imprint Lithography
     Stamp etch
Descum NIL residual
NIL Nanoscale Etching
Photonic Crystal Hole Etching
Selection of Other Nanoscale ICP Etching Processes
About Oxford Instruments Plasma Technology


Nanotechnology may be defined as the ability to accurately manipulate matter on nanoscale dimensions that is normally within the range 1nm to 100nm. This ability is enabling extension of the performance of traditional devices (such as the CMOS transistor), and the development of completely new devices and technology. The application of nanotechnology has increased substantially over the last few years, and it is important to note that there are very few fields of human technology that have not been benefited by it.

Application of Nanotechnology

Areas benefited by nanotechnology include the following:

  1. Medical – Examples include nano lab-on-chip for diagnostics, drug delivery, nano-tissue engineering
  2. Chemical –Examples include highly efficient nanocatalysts and nanofiltration
  3. Energy –Examples include nanotechnology in energy efficiency, and insulation, fuel cells, rechargeable batteries and photovoltaics
  4. Nanotech enhanced material for heavy industry –Examples include aerospace and construction
  5. Information and communication that include memories, novel semiconductor and optoelectronic devices, displays and quantum computing
  6. Consumer food, cosmetics, household, textiles, optics


This paper on nanoscale etching is most relevant to the nanotechnology area 5 but also finds uses in other areas especially 3 and 1. Etching is the selective removal of solid material through a mask to produce two or three dimensional structures in the fabrication of devices. The classic example is in etching steps required for monolithic integrated circuit fabrication that include complementary-metal-oxide silicon (CMOS) transistor chips with feature sizes on the micron scale and now much less. Indeed CMOS technology has long since progressed into the nanoscale.

Figure 1 taken from the International Technology Roadmap for Semiconductors (ITRS) 2010 update indicates this occurred in about the year 2003 while considering half pitch polysilicon gate widths for flash or DRAM technology.

This article will focus on the top down technique of ICP etching and will use in particular techniques and results for nano-imprint technology and photonic crystal fabrication, as well as illustrating the nanoscale etching capability for a broad range of materials and devices. The results are all achieved in Oxford Instruments ICP tools, demonstrating a strong capability in nanoscale etching.

Figure 1. From the ITRS 2010 update, plotting product half-pitch gate length against year of production [2]

ICP Tools

The ICP tools used for nanoscale etching processes described in this paper are all Oxford Instruments such as PlasmaPro System 100 configured with various ICP sources. A schematic of an ICP180 etch chamber is given in Figure 2 and a photograph of a PlasmaPro System 100 with the Cobra source is shown in Figure 3.

Figure 2. Schematic of the PlasmaPro System100 ICP180 tool

Figure 3. Plasmapro System 100 ICP Cobra

The ICP sources are of a cylindrical design with an RF power applied to a coil outside of an insulating device to generate a high density plasma, the ion density is generally more than 1011/cm3. An electrostatic shield around the ICP tube ensures that the ICP power is purely inductively coupled (i.e. ‘true-ICP’). This eliminates capacitive coupling, which can result in tube sputtering and stray ion trajectories. The wafers are clamped either mechanically or electrostatically to the temperature-controlled lower electrode. Helium pressure is applied to the rear side of the wafers to provide good thermal conductance between the chuck and the wafer. Smaller samples or pieces that are normally used for nanoscale etch research may be attached to a carrier wafer with a thermally conductive compound.

Oxford Instruments ICP systems provide an optional wide temperature electrode often useful in nanoscale etching. Electrode temperature is controllable over a range of -150°C to +400°. The systems are generally operated over a pressure range 0.1 to 100 mT by automatic pressure control. Gases are fed in through the top of the source or through a gas ring around the wafer electrode.

The PlasmaPro System 100 ICP180 is suitable for up to 100 mm diameter wafers. Oxford Instruments also offers an R&D tool, the PlasmaPro NGP 80 ICP65 having usable area 50 mm diameter, and tools with larger diameter capacity: the PlasmaPro System 100 Cobra (200 mm), the PlasmaPro System 133 ICP380 (300 mm) and the PlasmaPro NGP1000 Viper (450 mm). The Cobra source is suitable for R&D or production, whereas the other two systems are primarily for production.

Advantages of the Cobra Source

The advantages of the Cobra source are listed below:

  • The source has a large usable area when compared to the ICP180 source,
  • The source offers increased flexibility through options of an active spacer that allows independent control of ion distribution and offers optimized process uniformity across the electrode.
  • The source offers ICP source pulsing that minimizes wafer charging, for enhanced high aspect ratio etching. It may also be used for adjustment of ion radical ratios.
  • Bias power pulsing normally with low frequency power reduces notching at interfaces with insulators and reduces aspect ratio dependent etching (ARDE).
  • A close coupled gas pod is useful for gas chopped processes such as Bosch etching to reduce gas mixing in short process steps.

Difficulties and Limits of Nanoscale Etching

The reasons why nanoscale etching is tough are listed below:

  • Difficult transport of neutrals species in and out of ever smaller features
  • Increased effects of charging by ions and electrons as sidewalls get closer together.

While designing smaller devices, usually the lateral shrink is greater than the vertical shrink so the aspect ratio h/d increases as shown in Figure 4.

Figure 4. Design rules dictate increasing aspect ratio (AR) as critical dimension d shrinks for nanoscale devices

Neutral etching species and etch products move isotropically by diffusion unaffected by the perpendicular sheath field. As the aspect ratio increases, the number of collisions with the sidewalls increases. Each collision makes the progress of etching species slow towards the surface to be attacked and slows the escape of product species. Additionally, incoming species are shadowed by the top corners of the trench as shown in Figure 5.

Figure 5. Multiple sidewall collisions of a gas species (with low sticking coefficient) in a HAR feature

Optimally, the sticking coefficients of etching and passivating species will be carefully controlled. Figure 6 provides real examples where the sticking coefficients and passivation are not optimally managed.

Figure 6a. Excess sticking or wrong species: too much sidewall passivation.

Figure 6b. Insufficient passivation: bowed profile and underetching

The second main reason for the increasing challenge of nanoscale etching is the increased effects of charging by ions and electrons as sidewalls get closer together. Charged species experience a lateral force (charge q multiplied by the electric field E) which is inversely proportional to the square of the distance y from the sidewalls:

qE ∞ 1/y2

The proportionality constant is higher for conductive or polar material making up the sidewall. Hence, ions moving nearly vertically are deflected towards the sidewalls, and at higher aspect ratio there are a higher percentage of ions experiencing significant deflection as shown in Figure 7.

Figure 7. Deflection of charged species: Ions are nearly vertical on approach but experience a lateral force.

Conversely, electrons with their much greater mobility in the plasma move isotropically, both in the bulk plasma and close to surfaces, and they tend to build up at the mouths of openings in the surface as shown in Figure 8a. This negative charge repels further electrons and deflects positive ions at the top of the feature as well. If the substrate is conductive, then balancing currents can flow to alleviate such charge build up. However, if the substrate is insulating or electrically isolated like silicon-on-insulators (SOI) then charge build up will be worse as shown in Figure 8b.

Figure 8. Directional effects of charge

Figure 9 gives examples where positive ion deflection is causing “notches” at the top or bottom of the feature, or removing the passivation in the middle causing bowing.

Figure 9a. Notch at top of feature

Figure 9b. Notch at base of feature (SOI interface)

Figure 9c. Ion deflection causing bowing in the middle

Figure 9d. Ion deflection also causing trenching at base

Certain challenges faced with nanoscale etching are listed below:

  • Nanoscale etching usually exhibits steadily lower rates,
  • Additionally, in devices where the feature width is variable, the smaller features will be etching less deep than the wide features. This is well known by the term aspect ratio dependent etching (ARDE) and can pose a severe problem for some devices, necessitating re-design.
  • Another consequence of ARDE is etching depths that are non-linear with etch time.
  • Finally, process window for nanoscale etching is usually minimized, and of course, metrology and analysis become ever more tough as feature sizes shrink.

Nanoscale Etching by ICP

In this section many examples of successful nanoscale etching by ICP systems from Oxford Instruments will be presented and discussed.

Nano-imprint Lithography

Nano Imprint Lithography (NIL) is a versatile, economical, flexible and high throughput (parallel) method for fabrication of down to 10nm (and shrinking) structures even over large areas (wafers). It has applications in semiconductor memory, micro and nano fluidics, optical devices e.g. LEDs and lasers, life science, e.g. lab-on-a-chip systems, bio-sensors, radio frequency components, renewable energy and new nanotech devices. The basic process flow of NIL is shown in Figure 10.

Figure 10 is a simple schematic of the NIL process.

Figure 10. Schematic of the NIL process

Stamp etch

Requirements for a good stamp etch are vertical or very near vertical profiles, smooth sidewalls, uniform depths and critical dimensions (CD). It is also desirable to avoid trenching.

Figure 11 shows a chromium (Cr) masked quartz stamp etched in the System 100 ICP180 chamber using a C4F8-based plasma chemistry. 30nm features are etched to a depth of 200nm at a rate of 85nm/min ±<1% across a 2inch wafer. The selectivity over Cr was >170: 1. The profile is 89-90°, smooth and trench-free at the base.

Figure 11. High quality nanoscale quartz etching for NIL stamp.

The quartz profile was optimized by using the set electrode temperature as shown in Figure 12, while trenching was eliminated by using low enough DC bias as shown in Figure 13.

Figure 12. Simple profile control by temperature

Figure 13. Trench control by DC bias reduction

Cr is often used as a hard mask for the quartz stamp etch. Figure 14 shows a nanoscale Cr etch with features down to 70nm.

Figure 14. Nanoscale (70nm) Cr mask etch before quartz etch (picture courtesy of AMO)

Descum NIL residual

The second area requiring an etch process is the descum of the NIL residual. Some “scum” is present after the stamp presses into the NIL polymer and releases. Low scum is preferred. A ratio of HR/Hl 0.1 is considered ideal.

20nm of scum for a 200nm polymer film is shown in Figure 15.

Figure 15. Residual NIL polymer after stamping step

Requirements for a good descum are to remove the scum whilst reducing changes in profile and CD. ICP provides the best performance for descum, low pressure processing reduced isotropic etching and loss of profile and CD control.

Figure 16 is an example of a descum process of BCB polymer leaving 10nm intact using an O2-SF6 ICP process.

Figure 16. Nanoscale BCB lines descummed by ICP

NIL Nanoscale Etching

The prepared imprinted polymer it is mostly used as an etch mask. The requirements to the final substrate etch is based on the application and so are much more diverse than the stamp etch and descum.

Photonic Crystal Hole Etching

A photonic crystal is a periodic arrangement of holes in 1-d, 2-d or 3-d that creates a photonic band gap structure as shown in Figure 17. In a photonic crystal ‘forbidden’ wavelengths for light propagation arise much like forbidden electron energies within a semiconductor crystal. However the hole size must be proportional with the light wavelength λ.

Figure 17. A photonic crystal device: in-plane resonant cavity with 6-hole mirrors and its transmission plot (dashed line = simulation)

Examples of two dimensional photonic crystal hole etches are shown in Figures 18 to 21. These processes of course may be used for other nanotechnology applications such as those requiring ‘nanopores’.

Figure 18. Photonic crystal holes etched in InP using OI System 100 ICP180. Reproduced with kind permission of P Strasser, et al. ETH Zurich)

Figure 19. High aspect ratio Photonic Crystal holes in Silicon by Cryogenic ICP etching

Figure 20. Photonic crystal holes etched in SiO2 by ICP with C4F8-He chemistry

Figure 21. Photonic crystal holes etched in Ta2O5 by ICP with C4F8-O2 chemistry

The best process used a polymer free Cl2/N2/Ar chemistry. Cl2 is the etch gas, N2 provides sidewall passivation and Ar is used as a diluent. The OI wide temperature electrode is utilized with a set temperature above 200°C sample pieces are glued to a carrier plate and backside helium cooling is used. An etched depth of 2.9μm for 180nm diameter hole size was achieved at an aspect ratio of 16:1. The etch rate was 1.75μm/min

Selection of Other Nanoscale ICP Etching Processes

In Figure 22 to 24, examples are given of three ICP silicon etch processes with complementary attributes for nanoscale etching. The first is a room temperature process using a C4F8-SF6 gas mixture as shown in Figure 22. The second is the cryogenic process using a SF6-O2 gas mixture as shown in Figure 23. The third process is an HBr- O2 process that can offer very high selectivity over SiO2 achievable by controlled O2 substitution as shown in Figure 24.

Figure 22. 16nm Si lines etched by C4F8-SF6 ICP process ((Courtesy of AMO, Aachen). Profile control by C4F8% (right)

Figure 23. 22nm wide Si trenches etched to 169nm depth (7.5:1 aspect ratio) using pulsed LF ICP cryo process and a ZEP520A mask.

Figure 24. 34nm polySi gate etch, HSQ masked, stopping on 3nm SiO2 (Courtesy of AMO).


A review of ICP etching for nanotechnology has been given. The increasing difficulty of nanoscale etching has been discussed and it has been stated that current ICP technology is good for several years more to below 20 nm half pitch. New hardware developments may involve controllable frequency and pulsed plasmas, better substrate temperature control and advanced software control, for instance feedback loops using optical emission spectroscopy and other diagnostic techniques, parameter ramping. Many examples of high quality nanoscale etches by Oxford Instruments ICP systems have been given and we are continually adding to our ‘portfolio’ of materials etched and applications in the increasingly important area of nanotechnology.

About Oxford Instruments Plasma Technology

Oxford Instruments Plasma Technology provides a range of high performance, flexible tools to semiconductor processing customers involved in research and development, and production. They specialise in three main areas:

  • Etch
    • RIE, ICP, DRIE, RIE/PE, Ion Beam
  • Deposition
    • PECVD, ICP CVD, Nanofab, ALD, PVD, IBD
  • Growth
    • HVPE, Nanofab

This information has been sourced, reviewed and adapted from materials provided by Oxford Instruments Plasma technology.

For more information on this source, please visit Oxford Instruments Plasma technology.

Date Added: Nov 2, 2011 | Updated: Jul 15, 2013
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