The European Commission has reported on the NEON project which is developing nanocrystal technology to meet the need for more powerful flash memory.
Memory devices are coming under increasing pressure to become smaller, demand less power yet store more and more data to meet the demands of a range of modern microprocessor-based devices which currently run a variety of functions within cars, mobile phones, other wireless devices and industrial controls. Silicon nanocrystal-based memories could potentially become an evolutionary replacement for the polycrystalline silicon used in conventional programmable flash memory for today’s electronic equipment.
Electronic memory comes in a variety of forms to serve many purposes. Manufacturers use flash memory technology to store a chip’s software code and data, so the devices can be re-programmed several times during its development cycle. This makes it easy for the manufacturer to adjust to fast-changing market demands or correct software problems.
Unlike active computer memory, flash memory is non-volatile in that data stays in the chip after the device is turned off. A layer of polysilicon is buried in the gate oxide (SiO2) of a metal oxide semiconductor (MOS) device and thus able to store charges – electrons or holes. These charges constitute the ‘bit’ of information that can be written, erased or read by manipulating the terminals of the device. This so-called ‘floating gate’ transistor will retain data for ten years. New data can be written to a flash chip a million times before errors begin to occur.
However, it is becoming increasingly difficult to shrink flash memory chips. Although the insulating layer is effective, it is also a problem. The SiO2 insulators on flash chips today measure about 90 angstroms thick – an angstrom is one ten-billionth of a metre, or less than the width of a hydrogen atom – and can probably be shrunk to about 80 angstroms. Any thinner, and the electrons begin to leak out, leading to data corruption or loss.
In turn, the need for thickness makes power a problem. About 10 V must be applied to the floating gate to get electrons through in the first place – far more than is used to operate microprocessor transistors. And, if the size of the chip is reduced, the voltage intended for one cell might inadvertently affect a neighbouring cell – resulting in misrecorded data.
While these problems are manageable for the moment, making flash chips using traditional material when average component feature size reduces to 45nm – using new manufacturing processes set to begin in 2007 – is likely to be a tough task. Developers are therefore now experimenting with new materials and chip designs to get around the problem.
One option is to use a two-dimensional array of silicon nanocrystals to replace the polysilicon layer in the insulation layer. Being isolated one from each other, the nanocrystals are globally insensitive to leakage. This means you can shrink the insulator thickness and so the size of the cell and the voltage required to write or erase data.
The key challenge for researchers is getting nanocrystals of appropriate size and density at a very small and controlled distance – less than 5nm – from the electrodes of the device. If the nanocrystals are too dispersed, then the memory device will not hold a sufficient charge. If they are too far from the channel, then writing will require again large voltages.
The three-year Commission-funded NEON project therefore set out to show how a new generation of nanocrystal-based memory devices could replace conventional silicon using a variety of production methods, and explore how these devices could be manufactured reliably by producing a number of demonstrator devices.
“Nano particles have many good properties, but up to now they have never been integrated into any device,” says Dr Alain Claverie, project co-ordinator at the French National Centre for Scientific Research (CNRS) CEMES laboratory in Toulouse, and the prime contractor. “Since spatial distances of a few nanometres are critical for operating and studying the characteristics of such devices, we have developed an understanding of the underlying materials science and physics aspects of the formation of the nanocrystals.
“We used existing state-of-the-art microscopy characterisation tools and investigated new techniques that would help us measure nanocrystal size distribution, density and positioning within an insulating matrix. During the first half of the project, we demonstrated how three approaches – low-energy ion implantation, conventional ion implantation and molecular beam epitaxy – can be used to fabricate such populations of nanocrystals.”
A number of nanocrystal structures have been produced. “The first transistors have been fabricated and are currently under test. In the meantime, our industrial partners, having been very active during the project, are running their first batches,” adds Dr Claverie. “Globally, the project – due to end in 2004 – is on time, and we’ve had only small deviations from our initial plan. Most of the results we have already obtained have been either directly transferred to our partners, or submitted for patenting, or publication in international journals and conferences.”