Cadence Design Systems,
Inc. (NASDAQ: CDNS), the leader in global design innovation, announced today
that Hitachi has fully implemented a chip design in excess of 50 million gates
in just five weeks using the Cadence® Encounter® Digital Implementation
(EDI) System.
When designing large-scale, multi-million gate devices, the overriding concern
is turnaround time. The EDI System has the capacity to handle such large-scale
designs using the flat implementation flow. Major improvements to the design
infrastructure, such as multiprocessing and precise correlation throughout the
integrated design environment from implementation to signoff have enabled both
tremendous performance improvements and greatly enhanced quality of results.
“Today’s LSI has clearly shifted to become large scaled due to
the increased use of IP, while the market window has drastically narrowed,”
said Nobuo Tamba, Ph.D., general manager of the Design & Development Operation,
Micro Device Division, Hitachi Ltd. “Hitachi is continuously aiming to
provide the best-performance, best-quality products, so it is critical for Hitachi
to shorten the design time for large-scale LSIs. We adopted the Cadence Encounter
Digital Implementation System that brought us a remarkable design efficiency
to complete 10 million gates per week. We strongly believe that such a short
design turnaround time will be a significant advantage for our large-scale designs.”
The EDI System’s masterplan automatic floorplanner, high-speed prototyping
floorplan verification, and multi-threaded processing at each stage were major
contributors to the quick, five-week implementation of the 50-million-gate designs.
Along with the EDI System, Encounter Timing System enabled Hitachi designers
to quickly analyze and optimize timing for the large-scale design and lead to
faster design closure with a significant gain in productivity. The parallel
processing function in Cadence QRC Extraction contributed significantly to the
turnaround time reduction at the signoff stage.
“The EDI System represents a new generation of implementation solutions
with its fundamental new architecture and end-to-end multicore backplane to
address the requirements of very large-scale designs. It also delivers a complete
solution for low-power, mixed-signal, and advanced-node design, including full
embedded electrical signoff and DFM,” said Dr. Chi-Ping Hsu, senior vice
president of research and development for the implementation group at Cadence.
“We’re very pleased to have assisted Hitachi in creating this complex,
large-scale design, and this success is further evidence of Encounter enabling
breakthrough results for our customers.”
Posted July 14th, 2009
