The Institute of Microelectronics (IME), a research institute of the Agency
for Science, Technology and Research (A*STAR), today announced the launch
of a 3-Dimensional (3D) Through-Silicon Via (TSV) consortium to boost next generation
300mm wafer manufacturing capability for Singapore semiconductor industry to
meet technology and product needs. The consortium is a national initiative and
supported by the Singapore Economic Development Board (EDB) and A*STAR. IME
is teaming up with A*STAR's Institute of High Performance Computing (IHPC)
and Nanyang Technological University (NTU) in the consortium which consists
of two phases with a duration of eighteen months for each phase. IME is leading
Phase 1 of the consortium with participating companies that include Chartered
Semiconductor Manufacturing Ltd. (Nasdaq: CHRT, SGX-ST: CHARTEREDSC), STATS
ChipPAC Ltd. (SGX-ST: STATSChP) and United Test and Assembly Center Ltd. The
consortium will also leverage on strategic materials and equipment suppliers
for support in its endeavours.
For more than forty years, the semiconductor industry has relied on Moore's
Law to steadily increase the number of transistors by shrinking its geometry
thus allowing more functions to be designed in an integrated circuits (IC) chip.
The demand for miniaturisation and greater functionality in electronic devices
has driven transistor geometries so small, we are soon reaching the scaling
limit for semiconductor process technology. To put in perspective, the size
of the state-of-the-art transistor is in the order of 30 nanometres which is
about 3000 times smaller than the diameter of a strand of human hair. An approach
to circumvent the continued shrinking of planar ICs and scaling limitation by
stacking of IC chips or packages vertically is known as 3-Dimensional (3D) IC
integration. One of the enabling technologies for 3D IC integration is Through-Silicon
Via (TSV). TSV is a vertical electrical connection that passes completely through
a silicon wafer or chip to create 3D ICs or packages. The drivers for market
adoption of 3D ICs are increased performance, reduced form factor and cost reduction.
The goal of Phase 1 is to establish TSV design and processes for 200mm and
300mm TSV wafers 3D IC assembly, and train a pool of skilled personnel in the
semiconductor supply chain companies to support manufacturing of new products
with 3D TSVs. Phase 2 will demonstrate the integration of fully functional mobile
devices with TSV on a 300mm wafer process line.
Professor Dim-Lee Kwong, Executive Director of IME, said “The launch
of this consortium is timely as the semiconductor industry is grappling to find
solutions to extend the limit of transistor scaling beyond Moore's Law.
TSV opens up new possibilities to add complex and multi-functional features
to electronic devices by allowing integrated circuits or packages to be stacked
vertically. Over the last few years, IME has established deep competencies and
process capabilities for TSV carriers. What is unique in this consortium is
that we are able to gather key companies across the Singapore semiconductor
supply chain to establish cost-effective TSV process integration and manufacturing
capability on 300mm wafers to help accelerate the industry adoption of 3D ICs
with TSV.”
Dr. Raj Thampuran, Executive Director of IHPC, added “IHPC is delighted
to be a part of this consortium. Modelling and simulation capabilities will
certainly help to predict and optimise the performance in the complex design
of the TSV carriers.”
According to Professor Kam Chan Hin, Chair of School of Electrical and Electronic
Engineering at NTU, “This consortium has also provided Nanyang Technological
University a platform and new opportunity to work more closely with our partners
to bring academic research to the industry.”
Commenting on the value creation of R&D to industry, Professor Chong Tow
Chong, Executive Director of A*STAR's Science and Engineering Research
Council, added “One of A*STAR's objectives is to promote R&D
in fields that add value and grow the Singapore's manufacturing industry.
This consortium exemplifies how A*STAR research institutes work with companies
and institutes of higher learning to identify and develop next-generation capabilities
and technology to enhance the competitiveness of the semiconductor industry
in Singapore.”
Mr. Damian Chan, Director of Electronics Cluster at Singapore Economic Development
Board, said “Our vibrant semiconductor ecosystem consisting of IC design,
wafer fabrication, advanced assembly and test, and supported by a strong base
of suppliers offers a “Plug and Play” environment. The concentrated
ecosystem allows semiconductor companies to easily find their business partners
while enjoying access to the international market.” He added that “R&D
is the key to strong growth in the future. This industry-public research collaboration
is a unique opportunity for global players such as Chartered, STATS ChipPAC
and UTAC to leverage on each other's unique expertise and co-develop this
emerging technology to address the needs of the industry.”
Below are comments from some of the consortium members on the impact of the
3D TSV consortium in addressing the needs of the Singapore semiconductor industry
supply chain:
"Chartered understands that our customers need technology and solutions
that address their requirements in performance, cost and scaling. The 3D TSV
Consortium allows Chartered to focus on our core competency in TSV silicon integration
while leveraging the expertise of our partners in material research, design,
bonding, packaging and testing. The result is a proven 3D TSV infrastructure
from design to tested package," said Dr. Liang-Choo “LC” Hsia,
Senior Vice President of Technology Development at Chartered. "In joining
the consortium, Chartered will be part of the significant 3D TSV Infrastructure
value chain in Singapore."
“We believe the depth of expertise at IME and the consortium members,
combined with the knowledge we have on driving integration technology and flexibility
at the silicon level will provide important momentum in developing 3D TSV technology
into high volume IC packaging solutions. Our involvement with the 3D TSV consortium
will complement the research and development activities we have been working
on in advanced wafer integration technology,” said Il Kwon Shim, Vice
President, Technology Innovation of STATS ChipPAC Ltd.
“The new capabilities acquired from this strategic consortium will help
UTAC increase our service offerings to our customers. The innovative capabilities
and technologies will provide greater efficiencies in our delivery of customer
focused solutions. UTAC believes in partnering our customers to provide leading
edge semiconductor solutions through teamwork and enterprising spirit. We are
committed to meet our customer's expectations by providing quality products
and services through the creative involvement of our employees and a culture
of continuous improvement to offer higher value added services to our customers,”
said Dr. Anthony Sun, Group Vice President of R&D of UTAC.
Posted September 7th, 2009
