Mentor Graphics Corporation
(NASDAQ:MENT) today announced that STMicroelectronics (NYSE:STM), a global
leader in developing and delivering semiconductor solutions across the spectrum
of microelectronics applications, has used the Mentor Graphics Eldo circuit
simulator to characterize its first CMOS 32nm cell libraries. The companies
are long-term partners in the domain of advanced circuit simulation techniques
for digital and analog IP characterization. This cooperation was recently brought
to even higher levels, to ensure the successful development of a characterization
flow optimized for the leading-edge CMOS 32nm high-K metal gate low power ISDA
(International Semiconductor Development Alliance) process.
"STMicroelectronics is a leader in delivering a complete CMOS 32nm design
solution to our customers that optimizes design productivity for low power designs
without compromising the performance, quality or the silicon correlation. To
achieve this goal, we have built a reliable ecosystem with our long-term partner,
Mentor. We worked together to develop a robust solution for the design and characterization
of our libraries for our worldwide design teams," said Gérard Mas,
CMOS Libraries Group Director of the Technology Research and Development group
Because of low power design techniques, the variety of CAD tools to support
and the complexity of the deep submicron devices, the number of simulations
required to collect the data for a library characterization can be very large.
In parallel, the accuracy required for each simulation requires the designer
to use the most advanced MOSFET models (PSP) and the most accurate description
of the parasitic networks. To maintain productivity, the complete simulation
system must be optimized for that technology node. The Eldo simulator has been
able to handle this dramatic increase in model complexity and accuracy requirements
with runtimes at, or close to, those of previous design generations.
STMicroelectronics and Mentor also put together an intense collaboration program
to make the entire characterization process, which requires effective load distribution
and balancing on huge CPU farms, as smooth and robust as possible.
"Given the data volume, manual inspection is not an option. The entire
characterization must be a 'push-button' automated process, even
when each individual simulation is a challenge with these advanced technology
nodes and associated models. We developed quite a sophisticated infrastructure
to achieve this goal, and Mentor demonstrated the required reactivity, resources,
and engineering commitment to let us reach the desired productivity level,"
said Laurent Bergher, CMOS Standard Cell Libraries Group Manager at STMicroelectronics.
The available solution is now being used in production for both logic and analog
libraries (including ADCs, DACs, PLLs, Oscillators, and others) where simulation
accuracy and noise analysis are critical concerns. The close ST and Mentor collaboration
also enabled the sophisticated ageing models developed by ST process reliability
experts to be implemented in the Eldo simulator via the widely used Eldo UDRM
(User Defined Reliability Modeling) API.
"The close cooperation between Mentor and STMicroelectronics continues
to be very important to the strategies of both companies. ST is a world leader
in Analog and Mixed Signal Design and our work together helped Mentor provide
solutions in advanced areas such as the production-level environment for CMOS
32nm library characterization," said Robert Hum, Vice President and General
Manager of the Deep Sub Micron (DSM) division at Mentor Graphics.