Encounter Technology Accelerates Transition to 45- and 40-Nanometer Low-Power Design at Multiple Foundries

Published on May 7, 2009 at 8:41 AM

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced today that Gennum Corporation's (TSX: GND) Snowbush IP Group utilized the Cadence® Encounter® Digital Implementation System to develop the industry's first 45-nanometer SuperSpeed USB 3.0 PHY IP core. Encounter was used for timing closure and layout on the digital portion of the PHY. Introduced in March, the new IP from Gennum's Snowbush IP Group features an integrated USB 3.0 PHY and controller IP with a 5-gigabit per second (Gb/s) transfer rate in each direction. The Encounter Digital Implementation System helped Gennum's Snowbush IP design team quickly target the digital portion of the PHY to advanced 45- and 40-nanometer process technologies at multiple foundries, further expanding its market potential.

"The high-speed timing constraints of the PCS layer of the new USB 3.0 PHY require the highly capable design methodology offered by Encounter," said John Wilby, director of engineering-PHY, for the Snowbush IP Group at Gennum. "The move from a competitor's design environment to the Cadence Encounter Digital Implementation System took just three months from installation to first-pass silicon success. Key benefits with Encounter include its native signoff quality timing closure and support for advanced DFM rules in deep submicron technologies. In combination with low-power signoff, we also gained improved productivity, a high quality of silicon and ultimately faster time to market."

Wilby also noted that the fully integrated Encounter Digital Implementation System allowed Gennum to raise the bar on its design specifications and improve the competitive differentiation of its customizable family of IP cores through improved power savings and chip performance, reduced jitter, and optimized noise immunity.

The Encounter Digital Implementation System is a configurable and extensible high-performance, high-capacity, scalable design solution uniquely delivering flat and hierarchical design closure and signoff analysis, as well as low-power, advanced-node, and mixed-signal design solutions in a single integrated environment. The system also delivers interoperability with package, logic, and custom IC design. Cadence design-for-manufacturing (DFM) technologies are an integral part of the Encounter Digital Implementation System, enabling early identification, analysis and repair of yield-limiting design elements present at advanced nodes.

"Gennum's Snowbush IP Group has a strong track record of success, and we're pleased to play an integral role in the development of its latest high-speed family of customizable IP cores," said Chi-Ping Hsu, senior vice president of implementation research and development at Cadence. "This project was a success on multiple levels, but most notably it demonstrated that a full front-to-back design solution can be installed, ramped and used to deliver state-of-the-art advanced-node, low-power designs in a fraction of the time of previous solutions, with first-pass silicon success, lower risk, and faster time to market as the reward."

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