Reducing Manufacturing Time for Nano Engineered Substrates

Published on June 4, 2009 at 9:00 AM

The ability to continue increasing the scalability of the Dip Pen Nanolithography® (DPN®) process is now being assisted by a new design of very high density tip arrays (VHD).

Joe Fragala, Vice President of NanoInk’s MEMS facility, stated “removing the cantilevers allowed us to pack more tips into approximately the same area as our current 55,000 pen design. We have experimental designs being fabricated and tested which have millions of tips and this can reduce the fabrication time for a nano-engineered substrate from more than 1 hour per device to only a few minutes.”

This work is the result of a combination of NanoInk’s internal continuing efforts to promote massively parallel DPN and recent new, enabling technology for molding tips which has been licensed from the University of Illinois, Urbana Champaign.

The VHD tip arrays should be available for NanoInk’s DPN 5000, NSCRIPTOR™ and NLP 2000 systems in Q4 2009. Contact NanoInk for more information at

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