New QRC Technology Delivers Silicon-Accurate Parasitic Extraction for Improved Reliability of Advanced-Node Design

Published on June 9, 2009 at 11:16 AM

Cadence Design Systems, Inc. (NASDAQ: CDNS), enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics, announced today that the Cadence QRC extraction signoff technology has adopted a new interoperable data format, iRCX, developed by Taiwan Semiconductor Manufacturing Company (TSMC). This iRCX file includes comprehensive interconnect modeling data, enabling Cadence customers to perform accurate parasitic extraction signoff.

The availability of consistent manufacturing data to accurately model the demands of millions of transistors is essential to avoid catastrophic failures caused by an electrical short or an open circuit. The Cadence signoff analysis flow directly processes the iRCX database for parasitic extraction and electromigration (EM) verification rules that are used with QRC Extraction.

"iRCX plays the key role in enabling interconnect modeling related EDA applications, including parasitic extraction of Cadence QRC itself and electromigration analysis based on QRC's extraction results," said Tom Quan, deputy director of design service marketing at TSMC. "The new unified data format is part of TSMC Open Innovation Platform that provides designers the ability to select qualified EDA tools to match their design needs and ensure design accuracy for first time silicon success."

"By delivering foundry data directly to the scalable Cadence QRC Extraction software, the new TSMC iRCX process file allows our customers to quickly achieve consistent silicon-accurate parasitic signoff and EM analysis for their designs in a rapid cycle time," said Dr. Rachid Salik, vice president of research and development at Cadence Design Systems, Inc. "We continue to strengthen our relationship with TSMC and provide value to our mutual customers."

In addition to iRCX support, Cadence QRC reduces extraction turnaround time with its parallel processing technology. Designers benefit from improved productivity, consistent data, and silicon-accurate flows necessary to take designs to production.

Tell Us What You Think

Do you have a review, update or anything you would like to add to this news story?

Leave your feedback
Submit