Synopsys, Inc. (Nasdaq:
SNPS), world leader in electronic design automation (EDA), verification
and manufacturing, today announced the results of a collaboration with TSMC
under TSMC's Unified Design-for-Manufacturing (UDFM) architecture effort. This
collaboration enables designers to improve yields and accelerate time to market
through more accurate lithography simulation at 28 nanometer (nm) and below.
Through this joint effort, designers will now have access to the same technology
that is in production at TSMC. The solution offers a 28-nm lithography process
checking (LPC) engine, which includes Synopsys Proteus mask synthesis technology
and TSMC process models. Using an interoperable applications programming interface
(API), EDA design tools can now interface with the LPC engine to accurately
predict lithography hotspots in a given design before handing-off the designs
"TSMC is laying the groundwork for 28-nm process technologies and below
with the industry's first Unified DFM (UDFM) framework and LPC engine, which
is destined to become an important consideration," said ST Juang, senior
director of Design Infrastructure Marketing at TSMC. "At those nodes, it
will be exceedingly difficult for design tools to accurately assess lithography
issues without access to an exact copy of our tool chain and process models.
TSMC UDFM's 'copy exact' approach will not only provide actual lithography hotspot
data to designers, but will also open the door for all EDA vendors by enabling
encapsulated access to a large part of our manufacturing data."
Currently, the only way for design tools to access proprietary foundry data
is through abstracted models, which by necessity lose information in the translation
process. This can lead to overly aggressive checking during design, wasting
chip area and design time to correct false errors. In comparison, using the
new approach based on the encapsulated LPC engine, TSMC can provide EDA DFM
tools access to the TSMC Unified DFM Design Kit (DDK) that includes an exact
copy of the tool chain and process models used in the factory. In the case of
Synopsys, this allows PrimeYield LCC and ICC to create a comprehensive DFM solution.
PrimeYield LCC can be invoked within Synopsys' IC Compiler place-and-route system
to identify lithography hot spots with factory accuracy and offer fix guidance
for IC Compiler to auto-fix the hotspot.
"With UDFM and a LPC engine, Synopsys and TSMC enable designers to perform
more accurate lithography analysis. With copy-exact accuracy, designers can
be confident that they are neither sacrificing chip area, nor wasting time in
fixing false hotspots," said Saleem Haider, senior director of marketing
for physical design and DFM at Synopsys. "Together with TSMC, we are confident
that the EDA community will benefit from this open approach, and we look forward
to their participation in this Unified DFM framework."