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Strategy for Solving Technology Challenges in the Growing Wafer-Level 3D Integration Market

Published on July 13, 2009 at 8:40 PM

The Soitec Group (Euronext Paris), the world's leading supplier of silicon-on-insulator (SOI) and other engineered substrates for the microelectronics industry, announced today its strategy for solving technology challenges in the growing wafer-level 3D integration market with a family of proven processes and engineered substrates. The company has the combination of core technology know-how in wafer bonding and stacking, manufacturing infrastructure and high-volume experience, as well as strong IP to develop the building blocks required for wafer-level 3D integration. Soitec's 3D technology strategy is built on three pillars: Low-temperature Smart Cut(TM) technology, Smart Stacking(TM) technology and metal-to-metal direct bonding, currently in development.

"3D integration and wafer-level packaging technologies are promising and fast-growing segments of tomorrow's semiconductor industry. We expect 3D integrated semiconductors to grow at a CAGR of 50 to 60% during the period 2008 to 2015, mainly driven by memories, image sensors, MEMS, analog and CMOS logic applications," said Jerome Baron, principal analyst at Yole Developpement. "Despite the current economic downturn, the worldwide R&D activities linked to 3D integration innovation have reached unprecedented levels."

"We are working on making 3D technologies feasible and cost effective with an extensive and flexible offer. At the wafer level, both our Smart Stacking and Smart Cut technologies add significant value to 3D integration," said Andre-Jacques Auberton-Herve, president of the Soitec Group. "And when SOI wafers are used for CMOS processing, as demonstrated with imagers, end products are benefiting from higher yields and improved reliability."

Smart Stacking technology enables wafer-to-wafer level stacking of partially or fully processed circuits. The technique uses low-temperature oxide-oxide molecular bonding with specific surface conditioning, and high-precision wafer thinning. The low-stress wafer bonding process remains compatible with future requirements for submicron alignment accuracy. This technology is adapted for advanced semiconductor applications such as Back-Side Illumination (BSI) image sensors as well as via last 3D integration approaches. Using SOI as starting material, Soitec's technologies allow the successful stacking of extra-thin layers needed to achieve the highest through-silicon-via (TSV) interconnect densities.

Soitec's low-temperature Smart Cut process uses oxide-oxide molecular bonding and atomic-level cleaving to transfer mono-crystalline silicon films as thin as 0.1 micron onto partially or fully processed wafers. On this new material layer, a second level of devices can be processed and this integration can be repeated in an iterative mode. Transferring an extremely thin layer enables higher interconnect density, higher signal throughput and simpler TSV processing. Benefits include increased computing bandwidth, lower overall manufacturing cost, and power savings due to the reduced wiring distance between connected devices. This final benefit is well suited for producing advanced memory or CMOS logic 3D IC systems.

Additionally, Soitec's R&D work in metal-to-metal bonding in partnership with CEA/Leti (the Electronics and Information Technology Laboratory of the French Atomic Energy Commission) plays a key role in the company's 3D integration strategy. This approach presents the advantages of applying no additional pressure on the bonding stack and a lower thermal budget to guard against distortion and misalignment. The main application is in creating interconnections in the 3D stack during bonding.

At SEMICON West, July 14-16 in San Francisco, visit Soitec in booth #5448 in North Hall.

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