Taiwan Semiconductor Manufacturing
Company, Ltd. (TWSE: 2330, NYSE: TSM) today unveiled interoperable design
rule check (iDRC) and layout-versus-schematic (iLVS), two unified electronic
design automation (EDA) data formats, for TSMC 40 nanometer (nm) process technology.
TSMC iDRC and iLVS formats unify process design rules specification and technology
file generation, simplify data delivery, and ensure data integrity and interpretation.
Physical verification and analysis EDA applications, such as DRC and LVS tools,
which support iDRC and iLVS formats will be able to receive accurate design
rules data from the iDRC and iLVS files developed and supported by TSMC. The
TSMC iDRC/iLVS initiative is supported by major EDA ecosystem partners including
Cadence, Magma, Mentor, and Synopsys. The first 40nm iDRC/iLVS was developed
in collaboration with TSMC development partners, Mentor and Synopsys, and QA/validation
partners, Magma and Cadence. iDRC and iLVS are two of several interoperable
EDA interface formats co-developed between TSMC and its design tool partners
as part of the TSMC Open Innovation PlatformTM.
Design rules for advanced process technologies are more complex and require
detailed and accurate descriptions for correct chip layout creation and post-layout
analyses. TSMC collaborates extensively with the EDA partners in the iDRC/iLVS
initiative, defines the unified format based on TSMC process requirements, works
with EDA partners to implement the new format support in the tools, and closes
the loop by qualifying tool accuracy against actual silicon measurements, eliminating
data inconsistency, reducing customer tool evaluation time and improving design
accuracy. The qualification result is to be found in TSMC EDA qualification
program on TSMC-Online, the company’s customer portal. Multiple EDA companies
are participating in the qualification program.
“TSMC is the first foundry to collaborate with multiple EDA vendors to
create and qualify an interoperable physical verification format that optimizes
data delivery and interpretation between physical verification and analysis
tools and advanced process technologies,” said ST Juang, senior director
of Design Infrastructure Marketing at TSMC, “iDRC and iLVS are part of
the TSMC Open Innovation Platform that includes the Active Accuracy Assurance
Initiative. This new unified EDA data format provides designers the ability
to select qualified EDA tools to match their design needs, improve compliance
with TSMC processes, and ensure design accuracy for first-time silicon success.”
The TSMC iDRC and iLVS files will be available Q3 2009 in limited release and
to selected customers. General release to other customers is targeted for Q4
2009. Customers may access the technology files at the TSMC Online customer
design portal http://online.tsmc.com/online/
or contact their local sales and support representatives for details.