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Magma Announced Customers Pass 50-Tapeout Mark for Chips Designed at 45/40 nm Using Talus

Published on August 24, 2009 at 9:12 PM

Magma(r) Design Automation Inc. (Nasdaq:LAVA), a provider of chip design solutions, today announced Magma customers have passed the 50-tapeout mark for chips designed at 45 nanometer (nm) or smaller geometries using Magma's Talus(r) netlist-to-GDSII design implementation system -- more than with any other EDA supplier's implementation system. Talus, Magma's next-generation implementation platform designed specifically for chips at 45-/40-nm or smaller process nodes, is now widely used among Magma customers and its latest release, Talus 1.1, has demonstrated particular advantages for designs at the 45-/40-nm process nodes.

More than 55 percent of the 45- and 40-nm tapeouts were completed for networking and mobile applications. Other applications taking advantage of 45- and 40-nm technology include multimedia and graphics. In terms of geographic distribution, about 70 percent of the 45- and 40-nm tapeouts completed to date were by companies based in North America and about 25 percent by companies based in Japan or the Asia-Pacific region.

"As you might expect, networking and mobile applications represent the bulk of chips completed at 45 or 40 nm," said Premal Buch, general manager of Magma's Design Implementation Business Unit. "The designs completed so far at these geometries tend to be complex, in some cases approaching 100 million gates. Talus 1.1 with its COre(tm) (concurrent optimizing routing engine) and high capacity is ideally suited for implementing chips in these application areas which tend to push the performance envelope as well as have high gate counts."

Talus 1.1: The Fastest Path to Silicon for 45-/40-nm Chips

The Talus system was built to anticipate the unique requirements of chip design at advanced process nodes, and Talus 1.1 takes its capabilities even further. Since its availability was announced in May 2009, Magma customers have found Talus 1.1 to deliver significant improvements in runtime and timing convergence. It also achieves timing closure with no design-rule checking (DRC) violations and reduces total chip area significantly. Talus also offers a significant capacity advantage over competing systems which allows design teams to work on much larger blocks during the design process.

"Magma's raison d'etre from our beginning has been to provide designers with the best technology for advanced chips," Buch added. "That's why we closely track how many chips are taped out as the semiconductor community transitions to new process geometries. The transition to the 45-/40-nm nodes has again created an opportunity for Magma to expand market share. Of course, we are not stopping there and already have the foundation in place to support the next process node at 32/28nm. In fact, we are already seeing some of our customers working on 28-nm designs."

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