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EUV and Double Patterning to Maintain Lithography Roadmap for Next Several Technology Nodes

Published on November 12, 2009 at 8:07 AM

SEMATECH engineers and the industry at large continue to make progress in developing the infrastructure that will enable lithography for cost-effective manufacturing, according to papers presented at the 2009 International EUVL (Extreme Ultraviolet Lithography) and 193 nm Immersion Extensions Symposia in Prague, Czech Republic. This year's symposia were co-organized by SEMATECH in cooperation with IMEC, Selete, EUVL, and EUVA.

At the week-long duo of lithography events, an impressive attendance of nearly 400 top experts and researchers gathered to discuss progress on extending current technologies while building the infrastructure for future solutions. A combined set of 83 technical papers and 130 posters reported steady, measured progress in many key areas. At the same time, presenters highlighted various technology, infrastructure, and business challenges that the industry needs to address to successfully insert EUVL into manufacturing at the 22 nm half-pitch node.

“While the economy is down, attendance was up this year and we surpassed last year's number of registrations,” said Bryan Rice, director of lithography at SEMATECH. “I attribute this to a combination of the industry's critical need to address the cost and risk of developing EUV technologies and to a recognition that 22 nm solutions must be ready for insertion very soon – in 2013.”

During this year's EUVL Symposium, steady progress was reported for EUVL including:

  • Experts from Cymer reported laser produced plasma (LPP) sources generate 50 watts at intermediate focus (IF). This compares with a system requirement of 180 watts needed to expose 100 wafers per-hour in high-volume manufacturing.
  • SEMATECH researchers and research partners highlighted the key role the consortium has played in achieving significant advances in EUV resists, specifically through achieving 20 nm resist resolution images for chemically amplified resists and addressing the challenges of simultaneously meeting resolution, line edge roughness (LER), and sensitivity targets in a systematic way.
  • With EUVL moving closer to pilot line introduction, mask yield has become a critical focus and several chip manufacturers as well as consortia are using wafer printing and/or actinic aerial image review to characterize mask defects. Those printability studies show that the number of printing mask blank defects increases with decreasing feature size. About 50 percent of all inspected mask defects – mask blank defects, absorber defects, and pattern defects - print at the wafer level.
  • Lastly, the EUVL Symposium Steering Committee identified at the conclusion of the conference three remaining focus areas that the industry needs to work on to enable EUVL manufacturing insertion:
    • 1. Availability of defect-free masks, throughout a mask lifecycle, and the need to address critical mask infrastructure tool gaps, specifically in the defect inspection and defect review area
    • 2. Long-term source operation with 100 W at the IF and 5 megajoule per day
    • 3. Simultaneous resist resolution, sensitivity, and LER

“Good progress has been made toward achieving resist resolution and sensitivity targets, with some improvement in line edge roughness, and now chip manufacturers are demonstrating post-exposure resist processes that lead to significantly reduced line edge roughness,” said Stefan Wurm, EUVL Symposium co-chair and SEMATECH's associate director of Lithography. “With the world's leading-edge exposure tool for EUV resists learning, SEMATECH continues to enable the development of high performance resists required to demonstrate EUV manufacturability to our member companies and the industry.”

Key progress indicators outlined at the Immersion Extensions Symposium, include the following:

  • Immersion lithography has been extended to the 22 nm using a variety of approaches.
  • A wide variety of techniques including spacer, double etch, resist freezing processes, litho etch-litho etch, and source mask optimization were all demonstrated as viable double patterning approaches.
  • Invited speaker David Medeiros, of IBM, emphasized the explosion of masking at 22 nm using double patterning in his presentation entitled “Lithography on the Edge.” Sam Sivakumar of Intel predicted that future lithography processes will combine multiple approaches rather than a single winning technique in his presentation entitled “Technical and Manufacturing Challenges and the Prospect for HVM using ArF Pitch Division.”
  • Although progress is being made towards enabling the 22 nm node, the conference highlight was that the cost of ownership is of greater importance than the technical solution itself.

The 2009 International EUVL and Immersion Extensions Symposia are central elements of the SEMATECH Knowledge Series – a set of public, single-focused industry meetings designed to increase global knowledge in key areas of semiconductor R&D – and represent a great success in the history of SEMATECH-sponsored conferences as these technologies have evolved from tabletop experiments to fully adopted high volume manufacturing over the past half dozen years.

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