At next week's International Solid State Circuit Conference, imec
and Holst Centre present their newest breakthroughs in ultra-low power design
for wireless communications and wireless sensor networks, 3D design and in organic
electronics with an impressive number of contributions including 10 reviewed
publications and 6 contributions to tutorials and workshops.
Over the week, several news releases will be issued. You can find an overview
of the publications and news releases below:
A Wideband beamformer for a phased-array 60GHz receiver in 40nm digital CMOS
Imec researchers implemented a programmable analog baseband beamformer for a
4-antenna 60GHz phased-array receiver in 40nm digital CMOS. It is based on current
amplifiers employing shunt feedback. The phase shifter resolution is better
than 20°, with a bandwidth of 1.7GHz, power consumption of 35mW, input-referred
noise current of 170nArms and output IP3 of -6dBV.
A 30µW analog signal Processor ASIC for biomedical signal monitoring
Imec and Holst Centre present an analog signal processor ASIC for ECG signals.
In addition to the power efficient extraction of ECG signals, it proposes an
adaptive sampling scheme for data reduction, continuous-time electrode-tissue
impedance monitoring for sensing motion artifacts, and bandpower extraction
for beat detection. The ASIC operates on a 2V supply.
An analog organic first-order CT ?S ADC on a flexible plastic substrate with
Holst Cente, imec and TNO researchers present an analog organic first-order
CT ?S ADC, fabricated with a dual-gate organic electronic technology on plastic
foil. This analog circuit achieves a 26.5dB precision and performs at a clock
speed up to 500Hz. It consumes 100µA at15V. The circuit is designed following
a Vt-insensitive design strategy and applies high-pass filters for offset cancellation.
The active area is 13×20mm2.
Robust digital design in organic electronics by dual-Gate technology
A comprehensive study of dual-gate organic thin-film transistors targeting more
robust organic circuitry is performed by Holst Centre, imec and TNO researchers.
The difference between zero-Vgs-load and diode-load logic is studied and an
optimized design for both is presented. This new design is used in 99-stage
ring oscillators, to determine stage delays, and in 64b RFID transponder chips
yielding data rates of 4.3kb/s.
Design issues and considerations for low-cost 3D TSV IC technology
Imec researchers investigated key design issues of a low-cost 3D Cu-TSV technology:
impact of TSV on MOS devices and interconnect, reliability, thermal hot spots,
ESD, signal integrity and impact on circuit performance. The experimental verification
of their importance is presented and changes in current design practices to
enable low-cost systems are proposed.
A 2.4GHz/915MHz 51µW wake-up receiver with offset and noise suppression
Imec and Holst Centre present an envelope detector-based wake-up receiver front-end.
A double-sampling technique is implemented to suppress the 1/f noise and DC
offset, resulting in a lower output noise level and therefore a better SNR for
a given input level. The receiver consumes 51µW and occupies 0.36mm2 in
90nm CMOS. For 10kb/s OOK reception it achieves -69dBm and -80dBm sensitivity
at 2.4GHz and 915MHz respectively.
A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm
Imec researchers present a 2.2GS/s 4x-interleaved 6b ADC in 40nm digital CMOS.
Each ADC slice consists of a 1b folding stage followed by a pipelined binary-search
sub-ADC using dynamic nonlinear amplifiers for low power consumption and high
speed. Threshold calibration corrects for amplifier and comparator imperfections
and 31.6dB SNDR is achieved with 2GHz ERBW for 2.6mW power consumption.
A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS
An 8b SAR ADC is presented by imec and Holst Centre researchers. The 90nm CMOS
prototype achieves an ENOB of 7.8b at a sampling frequency of 10.24MS/s. The
use of asynchronous dynamic CMOS logic, custom designed capacitors, an internal
common-mode shift and low-leakage design techniques results in a power consumption
of 69µW from a 1V supply. The corresponding FoM equals 30fJ/Conversion-step
and is maintained down to 10kS/s.
A 5mm² 40nm LP CMOS 0.1-to-3GHz multistandard transceiver
A 5mm² 40nm digital CMOS multimode transceiver is presented by imec in
collaboration with Renesas and M4S. The 0.1-to-6GHz RX features 4 LNAs, 25%
passive mixer with IIP2 calibration, 5th order baseband filtering and a 50fJ/conversion
step ADC. It achieves NF down to 2.4dB, better than -30dB EVM and 50dBm IIP2.
A 0.1-to-3Ghz TX with baseband filter, voltage sampled mixer and PPA achieves
3.2% EVM at 0dBm output, with CNR down to -156dBc/Hz. The system uses two dual-VCO
5.9-to-12.8GHz fractional-N PLLs.
A 86MHz-to-12GHz digital-intensive phase-modulated fractional-N PLL using a
15pJ/Shot 5ps TDC in 40nm digital CMOS
Imec researchers present a 86MHz-12GHz digital-intensive reconfigurable synthesizer
with 100kHz to 2MHz bandwidth. It leverages a 15pJ/Shot 5.5ps 14b coarse-fine
TDC and a 6-to-12GHz dual-VCO set. The 0.28mm2 synthesizer features simple background
calibration, ?S noise cancelation, and digital phase modulation, and consumes
less than 30mW.