Facing financial constraints and serious technical challenges, the semiconductor
industry must practice creative collaboration to survive, grow, and link to
emerging industries, SEMATECH
President and CEO Dan Armbrust said in a recent keynote address to SEMATECH's
2010 Surface Preparation and Cleaning Conference (SPCC) in Austin, TX.
"Our success as an industry will depend on how well we innovate in collaborative
R&D," Armbrust said. "We need to be leaders in applying semiconductor
capabilities to emerging technologies."
Armbrust said that while the overall economy appears to be improving, the chip
industry continues to grapple with consolidation, rising R&D costs, flattening
revenue growth, and increasingly difficult technical targets. Given these conditions,
collaborations are becoming increasingly accepted as a necessary and cost-effective
business strategy, he noted.
"Collaboration is the path to survival and growth in a changing industry,"
Armbrust told approximately 150 conference attendees. "The challenges
are global and cut across industry sectors. Solutions require significant investment
and leveraged funding. We need to encourage new experiments in creative cooperation
– interdisciplinary and interregional collaborations, industry-university-government
alliances, and convergence with emerging technologies and industries."
Armbrust said the semiconductor industry has been a collaborative trailblazer,
forming consortia to share resources, costs, and risks; developing an industry
roadmap; holding forums for industry dialogue and consensus building; and creating
standards and infrastructure for major technology transitions.
"But we can do even better," he declared, by exploring new ways
to bring university research into the industry mainstream, developing new partnerships
between chipmakers and equipment and materials manufacturers to accelerate commercialization,
and forming collaborations with emerging industries in nanoelectronics, energy,
"Semiconductors are the foundation of these new industries," Armbrust
said. "Silicon fabrication can be applied to nanodevice fabrication. Our
material knowledge applies to material and thin film development. And our industry's
experience in material physics and fundamental science are relevant to smart
systems and device development."
Within the chip industry, Armbrust said SEMATECH has been redefining collaboration
by offering several new avenues of engagement:
- Program memberships that align consortial R&D with suppliers'
early product development needs. Two examples are SEMATECH's Resist
Materials Development Center and the Mask Blank Development Center at the
College of Nanoscale Science and Engineering of the University at Albany.
- Flexible program structures that allow chip-makers, suppliers, fabless,
and assembly/packaging companies to engage with SEMATECH to co-accelerate
development of commercial equipment and standard materials.
- SEMATECH's newly launched EUV Mask Infrastructure consortium, with
initial members committed to identifying and closing infrastructural issues
in EUV mask metrology
- Participation across industry sectors in developing 3D interconnects using
through-silicon vias—an industry game-changer that enables system productivity
growth apart from scaling and permits heterogeneous integration of new system-on-chip
- Environment, safety and health (ESH) initiatives to drive sustainable manufacturing
and reduce the industry's environmental footprint through energy and
resource conservation, supply chain alignment, ecofriendly process development,
and other measures. The International SEMATECH Manufacturing Initiative's
ESH Technology Center was formed to help device manufacturers and suppliers
pursue such objectives
- Collaborations with more than 80 universities worldwide to pursue projects
in critical logic and memory technologies – including such areas as
advanced materials, advanced devices and post-CMOS materials and structures.
Each university works with SEMATECH to co-develop processes that lead to commercial
Armbrust's comments preceded nearly 30 leading-edge technical presentations
from industry suppliers, FEP, and International SEMATECH Manufacturing Initiative
(ISMI). They included:
- An invited paper on FEP's success in using second harmonic generation
(SHG) to evaluate the effects of different surface cleans and passivation
treatments on indium gallium arsenide (InGaAs) was delivered by Dr. Jimmy
Price, Member Technical Staff. Price said the ability to accurately characterize
III-V surfaces and interfaces using SHGhighlights the potential of this technique
as an in-line metrology system suitable for InGaAs-based chip manufacturing.
"We now have a non-invasive method that process and device engineers
can rely on to monitor the quality of III-V surfaces and interfaces,"
- A benchmarking study by Michael Frisch, EHS Project Manager for International
SEMATECH Manufacturing Initiative (ISMI), on opportunities for recycling and
reclaiming fab and assembly test wastewaters. Frisch's study showed
recycling and reclamation opportunities for saving 5.1 billion gallons per
year (gpy) at member company fab sites, and 217 million gpy at the assembly
test sites. To realize this potential, the study recommended focusing on recycling
process rinse waters and reclaiming bulk wastewaters at member fabs.
- An analysis by FEP project manager Dr. Casey Smith of surface preparation
and cleans challenges for emerging technologies. Graphene appears to be a
promising channel material for non-silicon RF applications, although contaminants
must be controlled without oxidizing chemistries to avoid damage to the material,
Smith noted. For non-planar technologies such as multi-gate field-effect transistors
(MuGFETs), careful modification of the cleans sequence is needed to form residue-free
3D gates, especially for tight pitch layouts.
- Dr. Richard Hill, FEP device engineer, outlined the opportunities and challenges
if III-V MOSFETs. Hill said, "It's becoming more challenging to
continue to scale silicon without sacrifices in mobility and speed. You can
still scale with silicon, but it comes at a cost." By contrast, III-V
channels offer significant performance benefits, such as higher mobility and
enhanced drive current, which will allow continued scaling and performance
improvement. Hill qualified his optimism, however, by discussing the integration
challenges which remain, the biggest being dielectric interface quality.
For more than 10 years, SPCC has brought together leading researchers from
industry and academia to focus on challenges in advanced wafer and mask cleaning
and surface preparation. SPCC is part of the SEMATECH Knowledge Series—a
set of unique opportunities that focus on accelerating solutions for critical
challenges in the nanoelectronics industry.