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Posted in | Nanoelectronics

DesignWare DDR multiPHY IP from Synopsys Consumes Less Power and is Cost Effective

Published on April 9, 2010 at 2:38 AM

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced availability of the DesignWare™ DDR multiPHY which is designed to support a broad range of DDR SDRAM standards in a single PHY without sacrificing power consumption or silicon area.

These standards include LPDDR2, LPDDR/Mobile DDR, DDR3, DDR3L (1.35 V), DDR3U (1.2x V), and DDR2. The DesignWare DDR multiPHY enables designers to target different DDR types for a single chip through simple software control. This capability makes it extremely flexible to integrate into an extensive array of applications such as consumer electronics, mobile, networking, server, computing, commercial/industrial and automotive applications. The DesignWare DDR multiPHY supports data rates from 0 to 1066 Mbps and offers a DFI 2.1 compliant interface to the memory controller.

"Memory interfaces continue to be one of the key IP requirements we see in chip development. New standards such as DDR3, DDR3L and LPDDR2 are designed to meet system performance requirements while utilizing less power," said Dr. Keh-Ching Huang, Head of Marketing and IP Solution Planning at Global Unichip. "By supporting all facets of the DDR standards, Synopsys' unique DesignWare DDR multiPHY enables us to quickly incorporate the necessary functionalities into our SoC designs with less risk."

The DesignWare DDR multiPHY is architected for extremely low power consumption and features Delay Lock Loop (DLL) bypass modes for operation below 200 MHz. It also features an I/O retention mode that allows the chip's power supplies to be shut down completely while a small number of I/Os remain powered on to keep the external SDRAMs in self refresh mode. The DesignWare DDR multiPHY is designed to support the anticipated DDR3U standard operating at 1.2 or 1.25 V. Additionally, the DesignWare DDR multiPHY provides built-in data training circuits to enable in-system calibration, providing optimized system-level timing without material interaction with the memory controller.

The DDR multiPHY is a hard macro similar to Synopsys' complementary DDR PHY offerings.  Hard DDR PHYs offer significant benefits over "soft" PHYs or all digital PHYs such as:

  • Quick integration. All pieces of the PHY come from one vendor and have been verified together
  • Minimal timing closure problems. Known performance, proven in silicon
  • Better performance margins. Lower jitter, better duty cycle and more supply noise rejection
  • Area optimized circuits. Each bit path is designed with matched flight times on the data buses

"It has become as important to minimize power as it has to minimize overall chip cost in portable electronics," said John Koeter, vice president of marketing for the Solutions Group at Synopsys. "The DesignWare DDR multiPHY not only offers designers the flexibility to utilize any DDR SDRAM in the system through simple software control, it also features a power-conscious design that minimizes the silicon area and cost."

The DesignWare DDR multiPHY is a part of Synopsys' comprehensive DesignWare DDR IP offering that consists of digital controllers and PHY IP supporting DDR, DDR2, DDR3, Mobile DDR and now LPDDR2. The comprehensive portfolio of DDR IP supports leading 130-nm, 90-nm, 65-nm, 55-nm and 45/40-nm technologies. Synopsys helps lower integration risk by providing high-quality DDR IP solutions that have been implemented in hundreds of applications and are shipping in volume production.

Source: http://www.synopsys.com/

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