Site Sponsors
  • Strem Chemicals - Nanomaterials for R&D
  • Oxford Instruments Nanoanalysis - X-Max Large Area Analytical EDS SDD
  • Park Systems - Manufacturer of a complete range of AFM solutions

Synopsys Announces Availability of Platform Architect with Multicore Optimization Technology

Published on February 8, 2011 at 6:36 AM

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the broad availability of Platform Architect with Multicore Optimization Technology, a new solution for performance analysis and early definition of multicore system architectures in SystemC.

Using Platform Architect with Multicore Optimization Technology, designers of SoCs, chipsets and systems can capture hardware/software performance models of multicore system architectures in the early concept phase for robust performance measurement and trade-off analysis, months prior to software availability.

"Given the escalating costs of SoC design, system architects have a difficult task in defining the optimum system architecture to support all the desired application use-cases in a cost-effective way," says Rene van den Berg, system architect, car entertainment solutions, NXP Semiconductors. "The new Multicore Optimization Technology embedded in Synopsys' Platform Architect gives architects a clear understanding of the application and required features in an early stage of the project. With this insight on system performance, the hardware and software allocation of available resources, software scheduling scenarios and architecture dimensions and decisions, the overall design cycle time is greatly reduced."

The new Multicore Optimization Technology enables Platform Architect users to create task-driven workload models of the end-product application, known as task-graphs, enabling analysis and optimization of hardware/software partitioning and system performance. After hardware/software partitioning is finalized, architects reuse the same task-graphs and task-driven traffic for SoC-level architecture exploration and IP selection, as well as interconnect and memory subsystem performance optimization. Benefits include optimized multicore system performance, shorter evaluation times and faster time-to-market.

"Developers of multicore SoCs, chipsets and systems often tell us how worried they are about the risks of over-design and under-design, causing either uncompetitive products or expensive re-spins. They are realizing that multicore architecture analysis needs to be much more robust and start much earlier," says Frank Schirrmeister, director of product marketing, System-Level Solutions, Synopsys. "The new Multicore Optimization Technology for Platform Architect allows our users to find and resolve multicore performance issues while architecture changes are still feasible, avoiding costly re-work to hardware and software implementations."

Interaction between providers of hardware and software IP, multicore SoCs, chipsets and systems have become increasingly complex. Multicore Optimization Technology for Platform Architect greatly improves the effectiveness and precision of this collaboration by replacing written and verbal specifications with executable performance models of multicore system architectures. These can be easily shared between design chain partners without depending on final software and hardware.

Source: http://www.synopsys.com/

Tell Us What You Think

Do you have a review, update or anything you would like to add to this news story?

Leave your feedback
Submit