By Cameron Chai
Synopsys, situated in Mountain View, California, is a developer of software and IP deployed in semiconductor design, verification and production.
The company recently unveiled its Synplify Pro, Synplify Premier and Synphony synthesis support ideally suited for Xilinx's latest ISE Design Suite (IDS) 13. The suite supports its 28nm 7 series FPGAs. The FPGA equipment has a hierarchical project manager facilitating collaboration on the design with either a bottom-up or top-down version, incorporated into the SmartGuide incremental place-and-route (P&R) technology from Xilinx for rapid RTL-to-board implementation.
The synthesis increases FPGA implementation for deployment along with the Synplify Pro and Synplify Premier software. Its integration features include technology description, generation of control for multi-rate, multi-clock implementations, and supports device hardware such as multipliers, DSP units and memories. The three platforms jointly offer a solution that reduces hand-coding RTL time and risk in multi-million gate designs.
The Pro and Premier tools offer quick runtimes to enable high-density designs. The Premier software changes the gated clocks, generated clocks and tri-states prevailing in ASIC designs to target FPGA removing the need for changes in the RTL code. The software has SystemVerilog language and native supports for DesignWare IP, allowing the same IP code to be present within the new prototype.
The Synopsys FPGA equipment offers designers quick time-to-results in complicated FPGAs. The equipment includes the Pro logic synthesis, Premier advanced FPGA implementation and Identify integrated RTL debugger. FPGA tools also provide DesignWare IP support, links to high-performance VCS functional verification, integration with the company’s C and Model Compilers, and an ASIC-compatible synthesis flow suitable for FPGA-based prototyping.