By Cameron Chai
Synopsys, pioneer in IP and software for semiconductor development, production and verification has declared that through its collaboration with TSMC, the 28-nm Analog/Mixed-Signal (AMS) Reference Flow 2.0 of TSMC will validate the custom design solutions of Synopsis.
The reference flow 2.0 is a part of an all-inclusive 28-nm design system of TSMC. It offers new sophisticated functionalities to cut down the design cycle and enhance productivity. The new functionalities include Layout Dependent Effect (LDE)-aware and parasitic-aware design processes.
The LDE-aware feature speeds up the layout procedure by decreasing design iterations to include LDE. This procedure enables the modeling of the layout-dependent effects by the designers in the preliminary pre-layout design phase itself and speeds up time-to-tapeout.
The parasitic-aware flow uses process-based models for the accurate estimation of pre-layout interconnect parasitics, decreases layout iterations and the quantity of late-stage design because of parasitic effects. It allows designers study the impact of transistor parameter changes easily with no need for the modification of the layout, while considering the actual layout interconnect parasitics.
The comprehensive custom model of Synopsys was assessed for the AMS Reference Flow 2.0 of TSMC to give assurance to the customers that they can achieve their timeline and design quality needs. Vital modules of the solution include StarRC Custom parasitic extraction, IC Validator physical verification, Custom WaveView waveform analyzer, CustomSim FastSPICE circuit simulation, HSPICE circuit simulation and Galaxy Custom Designer custom implementation.