Posted in | Nanoregulations

X-FAB Approves Cadence Physical Verification System for its SoC Process Nodes

Published on October 10, 2011 at 5:51 AM

By Cameron Chai

X-FAB, which is an analogue and mixed signal semiconductor application foundry group has approved the Cadence Physical Verification System for all its process technologies.

The verification system which has been integrated with the Encounter and Virtuoso flows from Cadence includes design rule checking (DRC) and layout versus schematic (LVS) verification for all levels such as cell, block, transistor and full chip/SOC. The verification system can also integrate with all standardised end-to-end digital analogue and custom flows available in the industry thus ensuring more efficient methods of silicon realisation.

The main advantage of this verification system is that customers can physically verify their processes while remaining within the design and implementation environment thus increasing productivity. Teams involved in designing can verify and sign off DRC validation by identifying and solving errors in flows. This in return results in saving of time in long duration production loops and faster tape out. X-FAB’s approval enables the company to increase its performance and cater more efficiently to its mixed-signal customers.

According to John Murphy who is the group director of Cadence’s Alliance Marketing division, Cadence and X-FAB collaborated closely to effectively meet all the requirements of verification and adhere to all the parameters of sign off. This level of collaboration is essential for the development of the EDA360 vision program which is aimed at increasing the efficiency of the electronic design automation industry by providing functional verification tools and enhancing system level design.

Source: http://www.cadence.com

Tell Us What You Think

Do you have a review, update or anything you would like to add to this news story?

Leave your feedback
Submit