By Cameron Chai
Synopsys has declared that GLOBALFOUNDRIES has achieved silicon success for its first major 20 nm chip using Synopsys’ IC Compiler-Advanced Geometry (AG), which is the 20-nm version of IC Compiler.
The IC Compiler-AG is developed on Synopsys' IC validator in-design physical verification and Zroute technologies to provide a better double patterning technology (DPT) solution that reduces timing overhead and die size, while making the quickest path to design completion.
The tape out of this chip comprising a dual-core processor is a significant landmark in the partnership between GLOBALFOUNDRIES and Synopsys for the advancement of an extensive DPT-aware deployment solution and 20-nm rules. Through its selection for this large design, the IC Compiler has extended its technological dominance in the 20-nm design.
The complexity of the issues associated with managing capacity, performance, variability and power gradually increases for 20 nm process node similar to other process-node transitions. However, a new challenge for the 20 nm process node is DPT, which creates unprecedented problems to place and route instruments in producing a layout that fulfills the conventional aforementioned metrics as well as decomposes into dual alternating patterns without affecting device area or performance.
Synopsys' method to DPT maintains the performance of place and route tools and eliminates final-stage surprise, thus pacing the final tapeout. With its Zroute routing technology and DPT enhanced placement engine, IC Compiler efficiently created a DPT-aware layout that can be assessed and rectified for remaining DPT breaches utilizing IC Validator In-Design physical verification technology. GLOBALFOUNDRIES is closely working with Synopsys to provide this flow simultaneously during the launch of its 20-nm technology.