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UMC Certifies Synopsys’ StarRC Parasitic Extraction Solution for 28-nm Designs

Published on April 5, 2012 at 1:53 AM

By Cameron Chai

Synopsys’ parasitic extraction solution called StarRC has been qualified by UMC for its new 28-nm process technologies.

The StarRC solution offered silicon-validated accuracy on evaluation designs of UMC to fulfill the criteria of qualification for its sophisticated 28-nm High K/Metal and Poly SiON gate processes. UMC customers using the 28-nm processes can now access the StarRC technology files.

The StarRC solution is an important element of Synopsys’ Galaxy Implementation Platform. . It is a proven parasitic extraction solution for memory designs, analog/mixed-signal, custom digital and system-on-chip (SoC). The solution’s key 28-nm features are area-dependent via capacitance and resistance; improved parasitic extraction of layout-dependent device; polynomial-based diffusion resistance; new via etch and coupling effects; and sophisticated retargeting effects. Other sophisticated functionalities for 28-nm designs include the least netlist for the biggest SoC design signoff; proprietary reduction capabilities; improved multicore scalability and performance; and integrated Rapid3D technology for rapid, high-accuracy three-dimensional extraction.

UMC’s Vice President for Customer Engineering & IP Development Design Support Divisions, S. C. Chien stated that the validation of the StarRC parasitic extraction solution for the company’s 28-nm process technology reinforces the set of resources offered to customers designing 28-nm devices. Common customers can now commercialize their innovations by leveraging the company’s most recent foundry processes.

According to Antun Domic, Senior Vice President and General Manager for Implementation Group at Synopsys, UMC’s corroboration of the StarRC solution will help the company's customers to confidently bring their superior-performance 28-nm devices to the marketplace.

Source: http://www.synopsys.com/

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