CEA-Leti will have a major presence at DATE 2013, March 18-22, when it will chair seven sessions, organize the Special Day dedicated to “High-Performance Low-Power Computing”, co-organize a workshop on many-core architecture and present or co-present 10 papers.
In addition, Leti CEO Laurent Malier will speak at a March 19 special session: “Grenoble ecosystem to provide semiconductor alternative process for advanced CMOS”. www.date-conference.com/conference/session/3.0
The Design, Automation & Test in Europe conference, which will be held at Grenoble’s Alpexpo Conference Center, is the world’s leading event dedicated to electronic and embedded systems. Last year’s conference in Dresden attracted more than 1,400 experts and more than 800 exhibition visitors.
This year, DATE will include Special Days focusing on two areas that present new challenges to the system-design community: High-Performance Low-Power Computing, and Electronic Technologies for Smart Cities. The March 20 Special Day on High Performance Low-Power Computing will bring together leaders from semiconductors, mobile and consumer technologies, and high-performance computing areas to explore strategies for mastering future generations of computing nodes and enabling energy-efficient computing.
On March 20, the Special Day High-Performance Low-Power Computing chaired by Ahmed Jerraya features a keynote by John Goodacre from ARM and four sessions:
Other sessions chaired by Leti include:
On March 22, Leti and STMicroelectronics will organize a daylong workshop on Platform 2012 / STHORM, a many-core embedded architecture designed by ST and Leti as a scalable and customizable acceleration device.
Papers that Leti will present or co-present with partners, include:
- An Efficient and Flexible Hardware Support for Accelerating Synchronization Operations on the P2012 Many-Core Architecture
- Fast and Accurate TLM Simulations using Temporal Decoupling for FIFO-based Communications
- Performance Analysis of HPC Applications on Low-Power Embedded Platforms
- 3D Integration for Low-Power Computing
- Fast and Accurate Methodology for Power Estimation and Reduction of Programmable Architecture
- A Gate Level Methodology for Efficient Statistical Leakage Estimation in Complex 32nm Circuits
- Time- and Angle-triggered Real-time Kernel for Powertrain Applications
- Scan Design with Shadow Flip-Flops for Low Performance Overhead and Concurrent Delay Fault Detection
- Self-aware Cyber-physical Systems and Applications in Smart Buildings and Cities
- ARTM: A Lightweight Fork-join Framework for Many-core Embedded Systems
What: Design, Automation & Test in Europe
When: March 18-22
Where: Alpexpo Conference Center, Grenoble
CEA-Leti Booths: 53, 54, 39 and 42