Cadence Design Systems, Inc., a leader in global electronic design innovation, today announced that it has won two TSMC Partner of the Year awards during the TSMC Open Innovation Platform® (OIP) Ecosystem Forum. Cadence was presented with awards for both Soft IP and joint development of 16nm FinFET Plus (16FF+) design infrastructure.
TSMC determined the Soft IP award winner based on customer feedback, portfolio breadth, and strong technical support capabilities. The Cadence IP portfolio offers an extensive range of widely used protocols including DDR, PCIe, USB, Ethernet and HDMI.
The award for joint development of 16FF+ design infrastructure was given based on the early, in-depth collaboration between TSMC and Cadence on FinFET enablement and the development of this latest advanced node technology for next generation System-on-Chip (SoC) designs. Cadence tools certified for 16FF+ include Encounter® Digital Implementation System, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution, Quantus™ QRC Extraction Solution, Virtuoso® custom design platform, Spectre® simulation platform, Physical Verification System, Litho Physical Analyzer and CMP Predictor.
"We presented the awards to Cadence based on the quality results delivered through its Soft IP and 16FF+ solutions," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "Cadence has demonstrated its commitment to working closely with us to bring the highest quality design capabilities to IC designers around the world, and we look forward to continuing our partnership in the years to come."
"Cadence IP and tools enable customers to address their power, performance and area requirements so they can deliver the best quality designs within tight market windows," said Dr. Chi-Ping Hsu, senior vice president, chief strategy officer, EDA and chief of staff to the CEO at Cadence. "The award recognition from TSMC reflects our long-standing relationship and further demonstrates our ongoing commitment to delivering a strong IP portfolio and advanced node technology for next generation SoC designs. We've already begun working with TSMC on the 10nm certification process, and our tight collaboration continues to drive EDA innovation forward."
Source: http://www.cadence.com