Cadence Design Systems, Inc. today announced that Cadence® Innovus™ Implementation System has achieved v1.0 Design Rule Manual (DRM) certification from TSMC for its 16-nanometer FinFET Plus (16FF+) process.
The Innovus Implementation System successfully passed rigorous testing and has been validated by TSMC on high-performance reference designs in order to provide customers with a fast path to design closure. Additionally, Cadence and TSMC are collaborating on the certification of the Innovus Implementation System on the 10-nanometer (nm) FinFET process. The certification for the latest version of 10nm DRM and SPICE models is currently on target for completion in June 2015.
The Innovus Implementation System is a next-generation physical implementation tool that enables system-on-chip (SoC) developers to deliver high-quality designs with highly competitive power, performance and area (PPA), while accelerating time to market. The tool provides key technology for the 16FF+ process and supports floorplanning, placement and routing with integrated color-/pin-access-/variability-aware timing closure, clock tree and power optimization.
TSMC’s certification of Innovus Implementation System capabilities include:
GigaPlace™ placement technology that improves electrical and physical design closure
Integration with Cadence Quantus™ QRC Extraction Solution, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution, and Physical Verification System provides a fast path to design closure
“The Innovus Implementation System enables high quality results and fast path to design closure with its breakthrough placement and optimization capabilities and multithreading,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence. “TSMC’s certification of the Innovus Implementation System gives customers more confidence that their 16FF+ designs can meet aggressive PPA targets so they can deliver high-quality designs to market faster. We continue to closely partner with TSMC on the advancement of 16FF+ designs so our customers can stay at the forefront of silicon technology.”
“The Cadence and TSMC R&D teams collaborated closely on the certification of the Innovus Implementation System, and we are committed to enabling our mutual customers to deliver innovative, advanced-node designs to market,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “With this certification, designers can achieve rapid design closure while reaping the benefits of higher performance and lower power consumption on TSMC’s 16FF+ process.”
Source: http://www.cadence.com/