SEMATECH, in partnership
with the College of Nanoscale Science and Engineering (CNSE) of the University
at Albany, is pleased to announce that it has received a 300 mm Telius(TM) SP
UD system from Tokyo Electron Limited (TEL).
The Telius SP UD system is the latest generation through-silicon-via (TSV)
etch tool that has the versatility to investigate various chemistries to etch
vias ranging from sub 1 micron to tens of microns wide. The TSV RIE tool, which
is a critical component of all 3D TSV integration schemes, will be used in SEMATECH's
3D R&D Center at CNSE's Albany NanoTech Complex in Albany, NY.
"TEL was the first associate member of the 3D program and has been a valued
partner of the Interconnect division for many years. Given their experience
in deep silicon etching, we are very pleased to partner with TEL on this critical
aspect of developing 3D interconnects," said John Warlaumont, SEMATECH's
vice president of advanced technology. "Leveraging CNSE's pilot line to
establish a 300 mm 3D R&D center is a unique opportunity. It allows our
researchers to address the technical and manufacturability issues of creating
3D interconnects within a state-of-the-art CMOS environment."
Masayuki Tomoyasu, senior vice president and chief engineer for TEL, added,
"The integration of TEL's leading-edge 3D tools with SEMATECH's R&D
capabilities and know-how will bring significant benefits to our semiconductor
customers by refining our processes for TSV etch development."
Michael Tittnich, associate vice president for technical operations at CNSE,
said, "The strategic partnership between the UAlbany NanoCollege and SEMATECH
continues to demonstrate global leadership in accelerating cutting-edge nanoelectronics
education, research, development and deployment for the benefit of a growing
number of worldwide industry partners. This latest acquisition of Tokyo Electron's
next-generation TSV RIE tool expands CNSE's state-of-the-art 300 mm line, while
also illustrating the success of SEMATECH's 3D R&D program and its growing
presence and partnerships at CNSE's Albany NanoTech Complex."
Issues which have restricted 3D interconnects from entering high-volume manufacturing
encompass the front-end, assembly and packaging, and design and test. In an
effort to transcend these barriers, SEMATECH's 3D program has been working jointly
with chipmakers, equipment and materials suppliers, and assembly and packaging
service companies from around the world on early development challenges, including
cost modeling, technology option narrowing, technology development and benchmarking,
while also building industry consensus.