Magma(r) Design Automation
Inc. (Nasdaq:LAVA), a provider of chip design software, today announced
the availability of an integrated low-power IC implementation reference flow
for UMC's (NYSE:UMC) (TSE:2303) advanced 40-nanometer (nm) process.
This reference flow supports the UMC 40-nm process and the UMC 40-nm low-leakage
library. Based on the Magma Talus(r) IC implementation system and fully compliant
with the Unified Power Format (UPF), it allows designers to address low-power
nanometer design considerations during implementation and within a single environment,
maximizing quality of results (QoR) while reducing turnaround time. Similar
low-power reference flows for 90- and 65-nm processes are already available
"UMC and Magma's long-standing partnership has resulted in many productive
design support solutions for our customers," said Stephen Fu, director
of the IP Development and Design Support Division at UMC. "Our latest effort
is an integrated low-power IC implementation reference flow that gives designers
a means to address low-power issues during the implementation phase of 40-nm
"Our goal in working with UMC was to give project teams a way to address
low-power nanometer design considerations with an integrated low-power IC implementation
reference flow," said Premal Buch, general manager of Magma's Design Implementation
Business Unit. "The Talus platform's unique integration accomplishes that
goal while reducing overall turnaround time."
The Magma-UMC Low-Power Reference Flow
The Magma-UMC RTL-to-GDSII low-power reference flow includes the required scripts
and documentation for Magma users to move to UMC's advanced 40-nm low-power
process technology and offers timing closure without iterations to enable quick
A multiple-power domain is used to create different voltage domains with designated
purposes, including reducing leakage current and reducing chip power consumption
while meeting timing requirements. The reference flow provides MTCMOS power
switch insertion and placement for implementing a switched domain. It performs
automatic checking and insertion of level shifters and isolation cells into
the right locations in a domain, insertion of retention flip-flops in the domain
that can be powered down, and always-on buffering for retention of the control
signal in the switched domain.
In addition, Magma's placement engines complete all the standard-cell placement
in the design using features such as comprehensive congestion analysis and timing-driven
placement. Magma's clock tree synthesis constructs a minimum-skew clock tree.
With the GUI clock-tree browser, users can monitor the clock tree implementation
during the flow and can select the correct clock tree structures for their design.
After clock tree synthesis is completed, Magma's advanced routing engines complete
the routing, including signal and power routing, based on UMC's 40-nm design
Magma's integrated IC implementation solution and unified data structure as
the basis for the reference flow ensures better quality results for timing,
area, power, signal integrity and reliability while minimizing the design cycle.