STATS ChipPAC, a company that provides semiconductor packaging solutions announced a wide range of packaging options based on its fan-out wafer level technology platform.
The company makes use of the wafer level technology to shrink lithography nodes, to deal with complex designs and to augment performance requirements for consumer and mobile applications.
The fan-out wafer level technology offers more interconnects when compared to the fan-in technology. The wafer-level ball grid array (eWLB) is embedded into the company’s fan-out wafer level technology platform. With more than 100 million units brought from Singapore, the company is capable of manufacturing wafer formats of 200mm and 300mm using this technology.
eWLB has the design capability to house several interconnects and is not restricted by die size, which makes it suitable for achieving the required form factor and performance requirements of the portable and the mobile market.
The company has developed this technology to expand its range of package architectures required for multi-die, single die, system-in-package (SiP), three dimensional (3D), and ultra thin packaging. The evolution of this technology has resulted in delivering better thermal and electrical operating characteristics. eWLB proves useful to a wide range of market applications. A strong integration platform and an innovative design are some of the technology attributes of eWLB.
The company delivers several advanced package architectures, which has TSV and IPD with eWLB integrated into it. The short vertical TSV interconnections improve space efficiency for a higher electrical performance and smaller form factor.
Latest developments in eWLB, TSV, IPD and advanced technologies such as fcCuBE and die-to-die copper wirebonding for 3D packaging will be presented by STATS ChipPAC’s at the Electronic components and technology conference from May 31st to June 3rd in Orlando, Florida.
Source: http://www.statschippac.com/