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SMIC Unveils 40-nm Reference Flow for Low-Power Chips

Published on April 16, 2012 at 1:47 AM

By Cameron Chai

An advanced-node, low-power integrated circuit (IC) design reference flow has been unveiled by Semiconductor Manufacturing International (SMIC) using its 40-nm production process and Cadence Design Systems’ Cadence Encounter digital technology.

The SMIC-Cadence flow will help designers to rapidly create complex SoC designs for numerous low-power applications such as consumer electronics, including smartphones and tablets. Designs are automated with sophisticated power management features through this new IC design reference flow.

The new reference flow is a production-proven technique that is totally integrated to the comprehensive and integrated Cadence RTL to GDSII flow such as Cadence physical verification system, Cadence CMP predictor, Cadence QRC, Encounter power system, Encounter timing system, Encounter digital implementation system, Encounter conformal low power, and Encounter RTL compiler.

Cadence Design Systems’ Group Director for Strategic Alliances, John Murphy stated that SMIC and Cadence have partnered to help common customers to leverage a complete set of digital technologies, including physical verification, closed loop low-power verification, power domain aware physical synthesis, and flat power aware deployment with signal integrity and timing closure. The combination of the new design reference flow and SMIC’s 40-nm production process offers customers a unique approach to low-power design that improves their market-reach time with reduced power consumption.

The Vice President for SMIC Design Service, Tianshen Tang stated that design teams are now able to obtain faster time-to-volume for sophisticated low-power 40-nm designs by utilizing this, low-power, interoperable, common power format-based reference flow from RTL to GDSII flow.

Source: http://www.smics.com/

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