By Gary Thomas
California-based Tela Innovations, which provides semiconductor design solutions to facilitate scaling of manufacturing to nanometer process nodes, has introduced new standard cell libraries that can be used for 32/28 nm and 22/20 nm manufacturing processes.
32/28 nm and 22/20 nm cell libraries
The simple architecture of the new cell libraries not only facilitates customization as per customer requirements but also addresses the limitations imposed by lithography constraints on processes below 28 nm.
Tela’s solution is contrary to traditional belief that attempts to preserve previous generation’s complicated layouts considered to be necessary for area scaling. Tela’s transparent approach to layout design consists of tools to implement designs as per performance, power and area (PPA) requirements. This is complemented by providing tradeoff options in routability.
The architecture of the 32/28 nm libraries can be optimized for speed or density and support physical Electronic Design Automation (EDA) views, circuit simulation and schematics. They are equipped with storage and logic components and capability to execute arithmetic and register file functions. The libraries are also compatible with high-K metal gate, poly-silicon gate, and gate first and gate last processes.
The challenges faced in 22/20 nm processes are complexities in design imposed by the need to comply with Restricted Design Rules (RDR) and double patterning layout standards owing to the difficulty in etching 20 nm patterns with 193 nm light. The layout provided by Tela’s 22/20 nm libraries offers the cleanest splitting of pattern. The libraries also make provisions to employ beneficial new processes such as local interconnect through novel circuit and layout designs.