Apr 16 2014
Aprisa™ and Apogee™, ATopTech’s place and route solutions, have been certified for the version 1.0 Design Rule Manual (DRM) of TSMC’s 16nm FinFET process.
ATopTech, a leader in next generation physical design solutions, continued their ongoing collaboration with TSMC to optimize ATopTech physical implementation tools to support advanced designs in TSMC 16nm FinFET (16FF). The rigorous certification process ensures that ATopTech tools deliver satisfactory quality of results, including design correctness, routability, timing, power, area and manufacturability for designs in 16FF.
Aprisa and Apogee also passed TSMC’s Integrated Tool Certification, where all 16FF design rules and methodologies were validated within the ARM Cortex™ A15 quad-core processor design hardening flow. This certification includes all sign-off checks, including DRC/ LVS (design rule checking/ layout versus schematic), IR/ EM (voltage drop and electro-migration check), MVRC (multi-voltage rule check) and formal verification. Customers can request the Aprisa/Apogee Technology File for 16FF directly from TSMC for immediate 16nm design starts.
The 16FF certification program with Aprisa/Apogee delivers:
- Design enablement for 16FF DRM v1.0
- High-R layer optimization
- Vt min-area pessimism reduction
- CNOD (continuous OD) cell placement rules enhancement
- Low-VDD hold time fixing
- MiM (metal-insulator-metal) capacitor RC extraction and timing impact
- Standard cell pin access and routability improvement
“We find that many of our joint customers, especially those designing mobile devices, are moving to 16nm to increase the density of transistors and increase operating speed while also reducing power consumption,” said Jue-Hsien Chern, CEO of ATopTech. “Certification into TSMC’s 16FF flow continues to deliver the advanced technology our customers expect from ATopTech.”
“Design teams can be confident that the deep collaboration between ATopTech and TSMC will continue to deliver advanced process technology and accelerated 16nm FinFET development to joint customers,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division.
Source: http://www.atoptech.com/