Dec 18 2014
Synopsys, Inc., a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced the expansion of its collaboration with nanoelectronics research center imec to nanowire and other devices (FinFETs, Tunnel-FETs) targeting the 5-nanometer (nm) technology node and beyond.
The agreement enables Synopsys to deliver accurate, process-calibrated models for its Sentaurus™ TCAD (technology computer aided design) tools to semiconductor manufacturers for use during 5-nm technology node research and development. This latest agreement between imec and Synopsys follows successfully completed collaborations on FinFET and 3D-IC technologies for the 10-nm and 7-nm technology nodes.
"At imec, we focus on bringing the semiconductor industry leaders together to deliver future technologies," said An Steegen, senior vice president of process technologies at imec. "We are excited to expand our cooperation with Synopsys, the primary TCAD provider, to explore next-generation device and process technologies for 5 nanometer. This continued tight collaboration with Synopsys will enable us to tackle the physics and engineering of advanced devices and introduce a new device design infrastructure for the industry."
Working closely together, the joint Synopsys-imec team is investigating, among other topics, a vertical nanowire-nanosheet hybrid SRAM cell to target 5-nm technology. Early studies show the benefits of nanowire-nanosheet technology in density and performance compared to conventional FinFETs and lateral nanowires. Synopsys' Sentaurus TCAD tools that support this collaboration are used by technology development teams at foundries and integrated device manufacturers (IDMs) for device architecture selection, design and process optimization. Using early versions of Synopsys' TCAD models allows the imec project team to explore a range of topics including fundamental device physics (material science, quantum transport and strain engineering), middle-of-line (MOL) local interconnects and the optimization of parasitics. A significant part of the analysis involves full-3D process and electrical simulations to identify device and interconnect reliability solutions for these highly scaled circuits.
"This is the first time a process-calibrated TCAD simulation flow has been used to comprehensively study the process, device and circuit architectures so early in the technology path-finding process," said Anda Mocuta, logic device manager at imec.
The Synopsys TCAD tools used in this collaboration include the industry-standard simulators Sentaurus Process, Sentaurus Device, Sentaurus Interconnect and Raphael. 3D process structures are read into Raphael for extracting the resistance and capacitance of MOL structures and are combined with Sentaurus-derived compact models for circuit simulation with Synopsys' HSPICE® tool. This simulation flow enables technologists to evaluate the speed and power consumption of ring oscillators and other test circuits in the early stage of technology development, thereby closely linking technology development and selection with circuit-level targets.
"This expanded collaboration with imec builds on the success of previous collaborations to address key challenges at the 5 nanometer technology node," said Howard Ko, senior vice president and general manager of the Silicon Engineering Group at Synopsys. "Imec's advanced technology prototyping and characterization capabilities make it an ideal partner for our development and calibration of advanced Sentaurus TCAD models to address the significant technical and business challenges that our customers face in the development of 5-nm node technologies."
Source: http://www.synopsys.com/