Cadence to Demonstrate 10nm FinFET Process at TSMC 2015 OIP Ecosystem Forum

Cadence Design Systems, Inc. today announced it will be showcasing how it leverages the TSMC Open Innovation Platform^® (OIP) to optimize customer designs and manufacturing efficiency to ensure first-time product success on the 10nm FinFET (10FF) process at TSMC 2015 OIP Ecosystem Forum. The event is being held on September 17, 2015, at the Santa Clara Convention Center.

What:

Cadence is scheduled to deliver the following presentations in the EDA and IP tracks:

• Complexities in developing a high-performance DDR subsystem at 3200Mbps on 16FF+ and 10FF: 10 a.m., by Chung Huang, design engineering director, and Amjad Qureshi, vice president, R&D, DDR team
• Tackling coloring, cell pin access and variation at TSMC 10nm: 11 a.m., by Rahul Deokar, product marketing director
• Custom device array place, route, simulate prior to layout: 1:30 p.m., Rege Colwell, software architect, and Khaled ElGalaind, principal software engineer
• IC packaging-centric approach to design fanout WLCSP designs: 2:30 p.m., by Bill Acito, IC packaging product engineer
• Resolving 10G bandwidth issues for high-performance analog circuits on TSMC 10FF: 4 p.m., Randall Smith, design engineering director, and Chris Moscone, design engineering architect
• TSMC advanced-node EMIR analysis: 4:30 p.m., Hany Elhak, product management director, circuit simulation, and Suketu Desai, software engineering director
• Building silicon IPs and subsystems for automotive infotainment and ADAS applications: 5 p.m., by Charles Qi, system solution architect
• Cadence also plans to showcase its IP solutions in booth #411, including: Image/vision processing pedestrian detection
• Automotive infotainment
• In addition, experts from our design and verification tools groups will be at Cadence’s “Expert Bar” to answer questions and engage in thoughtful dialog.

Source: http://www.cadence.com