Sep 14 2015
Silvaco, Inc. today announced that TSMC has certified Silvaco's InVar electromigration (EM)/voltage drop (IR) analysis tools for 16-nanometer (nm) FinFET Plus (16FF+) Design Rule Manual (DRM) and SPICE model version 1.0 (v1.0). Silvaco's suite of power integrity signoff tools, InVar Power and EM/IR, provides users a complete solution, from early power analysis to signoff for digital gate-level designs.
The 16FF+ TSMC certification program with Silvaco's InVar tools encompasses:
- Accurate analysis for 16FF+DRM v1.0
- Complete coverage for all reliability rules for 16FF+ DRM v1.0
- Support iRCX in 16FF+
- Complex Ipeak rules that require accurate Td modeling
- Support for all power grid rules defined in DRM
- Complete rule check support for both supply and signal nets
"TSMC's 16FF+ process is a key technology foundation for a variety of applications such as mobile, cloud infrastructure and Internet of Things that will drive semiconductor demand," said David L. Dutton, Chief Executive Officer of Silvaco. "Silvaco's Invar tools provide a comprehensive gate-level power integrity signoff capability, which is critical at FinFET nodes. We are pleased to complete TSMC's stringent certification program for gate-level EM/IR analysis as this increases our customers' confidence to achieve first-pass silicon success. We look forward to building our relationship with TSMC as we collaborate to deliver new verification solutions at advanced process technologies."
"TSMC and Silvaco have collaborated to ensure that customers have confidence when they perform gate-level EM or IR-drop analysis," said Suk Lee, Senior Director of TSMC's Design Infrastructure Marketing Division. "Successful completion of the 16FF+ certification is a key milestone in our relationship, and we look forward to extending our collaboration at advanced process nodes."
Source: http://www.silvaco.com/