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Measuring Substrate-Independent Young's Modulus of Low-k Films by Instrumented Indentation

In this study the Young's modulus of low-k dielectric thin films is determined using an Agilent G200 Nano Indenter. The Hay-Crawford model is used to negate the influence of the substrate on...

http://www.azonano.com/article.aspx?ArticleID=2855 | 11 May 2011
Chemical Vapour Deposition Grown Carbon Nanotubes for Interconnect Technology

This paper looks at a simple method of growing controllable densities of interconnect type multiwall nanotubes with high proportions of Y-junction and multiple junction nanotubes across etched...

http://www.azonano.com/article.aspx?ArticleID=2036 | 14 Nov 2007
Binding of Carbon Nanotubes Dispersed by Optical Tweezer on Silicon Surface

Optical tweezers cum microdissection combi was used for dispersion of carbon nanotubes, The resultant nanotubes were functionalized with thionyl chloride and then successfully bound to functioalized...

http://www.azonano.com/article.aspx?ArticleID=1594 | 10 Jun 2006
Carbon Nanotubes and the Electrical, Thermal, Mechanical and Other Useful Properties of Carbon Nanotubes by Cheap Tubes

Carbon nanotubes have a host of unique favourable properties. These properties including high electrical conductivity, flexibility, elasticity, thermal conductivity, aspect ratio and absorbance, very...

http://www.azonano.com/article.aspx?ArticleID=1564 | 17 May 2006
Atomic Layer Deposition for Nano & Macro-Electronics (ALD) for Nanoelectronics – Advantages, Services and Facilities Offered by CPI

Cenamps is putting together an epitaxy manufacturing process and cleanroom for producing silicon wafers and microsystems. These facilities will be will be avilable for R&D on advanced Epitaxy...

http://www.azonano.com/article.aspx?ArticleID=1458 | 28 Nov 2005
New Material May Replace Traditional Metal at Nanoscale Widths

The unique properties of thin layers of graphite-known as graphene-make the material attractive for a wide range of potential electronic devices. Researchers have now experimentally...

http://www.azonano.com/news.aspx?newsID=11878 | 4 Jun 2009
UCSB Professor Elevated to IEEE Fellow for Work on Nanoscale Interconnects

The College of Engineering at University of California, Santa Barbara (UCSB) is proud to announce the elevation of three of its faculty members to the rank of Fellow of the Institute of...

http://www.azonano.com/news.aspx?newsID=24125 | 20 Jan 2012
Imec Sets Major Step Towards 20nm Half Pitch Interconnects

Imec sets major step towards 20nm half pitch interconnects with the realization of electrically functional copper lines embedded into silicon oxide using a spacer-defined double patterning...

http://www.azonano.com/news.aspx?newsID=18504 | 13 Jul 2010
SEMATECH Workshop Writes Needs List for Managing Stress in 3D Interconnects Using TSVs

A recent SEMATECH-sponsored workshop has identified the development of a modeling and simulation methodology as a critical need for managing stress in advanced 3D interconnects using...

http://www.azonano.com/news.aspx?newsID=16912 | 8 Apr 2010
Research into Graphene Nanoribbons Provides New Reasons for Using it as Interconnects In Future Computer Chips

Recent research into the properties of graphene nanoribbons provides two new reasons for using the material as interconnects in future computer chips. In widths as narrow as 16 nanometers,...

http://www.azonano.com/news.aspx?newsID=12873 | 29 Jul 2009

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