SUSS MicroTec AG has introduced nano PREP, a surface activation and wafer-to-wafer bonding method that enables semiconductor materials, such as silicon on insulator (SOI) and strained silicon using direct wafer bonding (DWB), to be created.
Patents are pending on the technology that reduces the process temperature from 1000°C down to 200°C by incorporating an atmospheric pressure plasma to generate a molecular level surface modification. This allows new applications for wafer level integration of CMOS and MEMS or CMOS and nanotechnology.
In traditional direct wafer bonding, or fusion bonding, the high temperature anneal that is required limits the types of materials that can be joined. For applications using fully processed wafers such as CMOS and MEMS devices the maximum allowable temperature is less than 400°C. The nano PREP technology will now make this possible.