Scanning Microwave Microscope (SMM) has been designed to exploit the flexibility and outstanding accuracy of a vector network analyzer (VNA) to measure impedance, especially the measurement of quantitative capacitance on a dielectric sample. It is also possible to engineer the SMM to determine differential capacitance (dC/dV) through the application of a low-frequency (RF) modulation signal to the microwave (MW) measuring signal.
Dopant Profile Measurement Module
The instrument for dC/dV measurement is referred to as the dopant profile measurement module (DPMM), which can be coupled to KLA Tencor VNA instruments. Keysight’s SMM system comprises of a standard AFM unit and a VNA unit, such as the performance network analyzers (PNA) series.
It also features a lock-in amplifier and a DPMM module for dC/dV measurement. Figure 1 shows the schematic representation of the components of a typical SMM system, which enables simultaneous capacitance and dC/dV imaging.
Figure 1. A simple block diagram of the SMM configuration for capacitance and dopant measurement.
Within the DPMM, the MW signal obtained from the VNA can be divided into two parts. The first signal is amplified and utilized as the local oscillator signal (LO) for the dC/dV mixer, and the second signal is amplified and transmitted to the AFM probe tip through the main arm of the coupler. An external source, such as a function generator (for instance, the MAC Mode III controller on the KLA TencorAFM), is also used to apply an RF signal to the AFM probe tip.
The RF signal induces changes in the capacitance of the sample, which causes reflection and modulation of the MW signal at a rate comparable to the RF frequency. This reflected, modulated MW signal is subsequently divided into two components. The first part is amplified and transmitted to the DPMM internal mixer, where it is mixed with the LO signal and subsequently demodulated. A lock-in amplifier for dC/dV amplitude and phase signal is used to further process this demodulated signal. The second part is amplified and transmitted to the VNA receiver to measure the sample’s capacitance.
Imaging of Dopant Structures of Semiconductor Devices
The mobile charge carrier in the doped region of semiconductor devices can either deplete or build up within the proximity of a contact electrode based on the application of the DC bias. An AC voltage (Vac) is applied around a fixed working potential (Vdc). This induces a change in capacitance dC in response to the modulation voltage (Vac) (Figure 2).
Vdc is typically selected at that point where the slope of the C-V curve is the largest and is around the flatband voltage, enabling optimum sensitivity. Under these conditions, a lower dC/dV value denotes higher carrier concentrations, while a higher dC/dV value represents lower carrier concentrations. Also, p- and n-type Si have the same magnitude of dC/dV but of opposite sign for identical carrier concentrations.
Figure 2. Capacitance vs voltage plot for n-doped (gray) and p-doped (red) semiconductors. For the same ac modulation signal applied, the change in capacitance is larger for lower doping density (solid line) and smaller for higher doping density (dashed line). For p and n-doped samples they are identical in amplitude, but opposite in phase.
The reflected MW signal’s modulation index (the modulated signal’s phase and magnitude measured by SMM) can be utilized in the characterization of the type and structure of dopant in semiconductor devices. The sample illustrated is from a BiCMOS silicon IC. A hydrofluoric etch process is used to delayer the BiCMOS silicon IC in order to reveal the doped regions in the active devices.
The IC process stack comprises a lightly doped p-substrate with an epitaxial layer that is roughly 3.0 µm-thick. Highly doped N+ and P+ buried layers are placed at the interface. The contacts and wells of the active devices are formed by shallow doping of different impurities. Figure 3 shows a cross-sectional view for reference. Figure 4 shows a 3D topography image of the chip surface by AFM.
Figure 3. A cross-sectional view of the BiCMOS silicon IC sample which has been delayered to reveal the doped regions within the active devices. The IC process stack includes a lightly doped p-substrate with an epitaxial layer approximately 3.0µm thick. Highly doped N+ and P+ buried layers are positioned at the interface. Shallow doping of various impurities forms the wells and contacts of the active devices.
Figure 4. Topography image of an IC sample.
Capacitance (PNA amplitude) and dC/dV images of an IC sample using the SMM are presented in Figure 5. Figure 5a depicts the capacitance image, showing the variations in the varied shallow doping that build devices within the active regions. Figure 5b shows the dC/dV phase image with a dramatic contrast difference, confirming the presence of sub-surface highly doped layers. Figure 5c shows a vertical line profile across the phase image (represented as green line in Figure 5b).
The measurement reveals that the various bands in the IC are of 1800 different in phase, suggesting the domination of opposite charge carriers at these two different regions of the sample, in-line with the existing bands of underlying n-type buried layer (NBL) and p-type buried layer (PBL) of the active components. The regions of the NBL and PBL can also be revealed by overlaying the circuitry map atop the PNA amplitude image. A slight variation in capacitance can also be observed between the two regions.
Figure 5. Capacitance (a), dC/dV phase (b), phase line profile (c), and design layout of the IC sample.
The topography (a), dC/dV amplitude (b) and phase (c) images of a tinier region on the surface are shown in Figure 6. In this case, the dC/dV phase provided two types of information: the opposite carriers between the bands and the subtle differences caused by changes in each individual components. These differences can be observed when looking at only the n- or p- type region by appropriate adjusting the contrast, as depicted in Figure 6d.
Figure 6. Topography (a), dC/dV amplitude (b) and phase (c) images of the IC sample. (d) is a zoomed region on (C) showing the small variations of phase corresponding to individual structures.
The aforementioned results clearly demonstrate the ability of SMM to measure the capacitance and dopant profiling in semiconductor devices. The interaction volume and the penetration length of the microwave signal allow identification of certain structures underlying the surface.