Ultra-Thin Dielectric Diffusion Barriers from Novellus Increases 32nm Interconnect Performance

In order to support the RC delay scaling required by the International Technology Roadmap for Semiconductors (ITRS), process designers have focused their attention on reducing the permittivity of dielectrics used in the interconnect stack. Research has shown that significant reduction in the permittivity of the overall interconnect stack can be achieved by focusing on the material properties and deposition method of the dielectric diffusion barrier.

65nm device cross section showing diffusion barrier and contact etch stop deposited using MSSP. Image courtesy of Intel.

Innovative deposition and pre-treatment technologies have been developed using Novellus' (NASDAQ:NVLS) patented multi-station sequential processing (MSSP) architecture to create ultra-thin dielectric barriers that minimize impact on RC delay while ensuring stringent electromigration (EM), dielectric breakdown, and line-to-line leakage requirements are met.

The unique film properties derived from MSSP have led industry-leading manufacturers of logic and memory devices to implement dielectric diffusion barriers fabricated using the Novellus VECTOR(R) PECVD system. Figure 2 shows a 65nm device cross section with both dielectric diffusion barrier and contact etch stop layers deposited using the MSSP approach.

"The dielectric diffusion barrier is a critical layer in the interconnect stack due to the role it plays in determining device reliability," said Kevin Jennings, senior vice president and general manager of Novellus' PECVD business unit. "Novellus' diffusion barrier films meet today's performance needs and have been demonstrated to meet the EM and dielectric breakdown requirements for future technology generations."

For more information regarding the use of thinned dielectric diffusion barriers to scale RC delay, check out www.NovellusTechNews.com/Thin-Barriers.aspx.

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