Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global design innovation, said today that its Cadence® Encounter® Digital Implementation System for advanced RTL-to-GDSII chip design has enabled STMicroelectronics to equip their worldwide design teams with 65- and 40- nanometer production flows that provide industry leading performance and capacity for multi-million instance, high-performance SoC designs in the consumer, computer peripherals and wireless markets. In addition, STMicroelectronics' and Cadence are collaborating on a next-generation 32nm design platform, based on STMicroelectronics' state-of-the-art cell libraries, targeting low power, mixed-signal, and advanced system-in-package (SiP) design capabilities.
"We've been working closely with the Encounter product family and Cadence R&D for several years now, increasingly adopting Encounter digital implementation for STMicroelectronics' most complex SoC products," stated Philippe Magarshack, group vice president at the Technology R&D group of STMicroelectronics.
Encounter Digital Implementation System offers advancements in silicon virtual prototyping, die-size exploration and RTL and physical synthesis, providing improved predictability and optimization in early stages of the flow. In addition, the new system delivers end-to-end parallel processing, automated floorplan synthesis, innovative hierarchical abstraction technologies, end-to-end multi-mode, multi-corner (MMMC) optimization, variation-tolerant and low power clock tree and clock mesh synthesis, high-capacity placement and optimization, 32-nanometer routing, DFM-aware implementation and chip-and-package co-design.
"With the new performance and capacity improvements of Encounter Digital Implementation System we have significantly increased our usage, and are deploying Encounter for our 55-, 40-, and 32-nanometer SoCs," said Thierry Bauchon, R&D Director for STMicroelectronics' Home Entertainment Group.
"Cadence Encounter Digital Implementation System leads the way in performance, capacity, and breadth of solution for today's complex, high-performance, low power, mixed-signal, and advanced node designs," said Chi-Ping Hsu, senior vice president of Research and Development for the Implementation Products Group at Cadence. "Working in collaboration with world-class design companies such as STMicroelectronics, we've broken new ground in the digital design arena and delivered significant advantages to our users in QoS (Quality of Silicon), time-to-market, and overall risk reduction."