A recent SEMATECH-sponsored workshop has identified the development of a modeling and simulation methodology as a critical need for managing stress in advanced 3D interconnects using through-silicon vias (TSVs).
The one-day conference drew more than 50 technologists from 26 companies and institutions in the US, Asia and Europe to SEMATECH’s facility at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany. The purpose of the workshop was to develop characterization and modeling approaches for mechanical stress management for 3D TSV products, and to drive consensus and support for these techniques across the industry.
“There are many different approaches to implementing 3D, and they all require an analysis of the mechanical stresses, and that analysis may be decisive in determining which approach is chosen for which application. Enabling designers to perform the analyses and trade offs is therefore critical for adoption of 3D technologies," said Sitaram Arkulgud, director of SEMATECH’s 3D Program.
“There are many sources of mechanical stresses, including copper filled TSVs, thinning of wafers to a few tens of microns, tier-to-tier bonding, and chip-package interactions,” added Larry Smith, workshop chair. “These stresses have the potential to modify device electrical characteristics, affecting product functional and parametric yield, and also to cause long-term reliability problems. Successful implementation of 3D interconnects requires that these stresses be properly characterized and managed throughout the design and manufacturing supply chain.”
At the 3D Workshop, attendees divided into two breakout sessions covering package and silicon domains, and addressing characterization/metrology and modeling/simulation challenges.
The characterization/metrology team reported:
- 3D technology- and fab-dependent materials characteristics are needed as input data for modeling and simulation
- Multi-scale materials characterization, analogous to multi-scale modeling, is critical for enabling predictive simulation of stress distribution across a device layout.
- Most of the needed characterization techniques for materials data are currently available.
- Specially designed test structures, including TSVs and field effect transistors (FETs), are essential.
The modeling/simulation team recommended:
- Compact models covering all components of layout-dependent stress should be developed.
- Package scale simulation tools based on finite element modeling (FEM) are required to generate boundary conditions that describe packaging-induced stress at all faces of the die.
- An integrated methodology that incorporates all components of stress and relates them to electrical device characteristics can be deployed.
Follow-up meetings are being planned to evolve these and other recommendations.
Potential topics include:
- Advanced characterization techniques
- Presentation of available simulation flows
- Layout of test structures for calibration and validation