Synopsys has reported that Synopsys design implementation tools has earned Phase I Certification from TSMC for its 20-nm process.
Synopsys design implementation tools have been certified for TSMC’s 20-nm design rule manuals (DRMs) and SPICE models. The certified products are Synopsys' Galaxy Custom Designer for custom implementation; StarRC for extraction; IC Validator for LVS and DRC; and IC Compiler for physical design.
Certification of the Synopsys PrimeTime suite for static timing analysis is under progress. Certification includes all the associated 20-nm technology files such as interoperable process design kit, extraction rundecks, verification runsets, and routing rules.
Synopsys' Galaxy Implementation Platform provides complete support for TSMC's new set of 20-nm design rules. StarRC is a parasitic variation modeling solution deals with the impact of advanced patterning technology caused by misalignment of mask and other key technology prerequisites.
IC Validator is Synopsys' latest native graph-based coloring that ensures in-design integration and layout decomposition with IC Compiler to achieve precise 20-nm design signoff.
IC Compiler with correct-by-construction innovative-patterning-clean routing and innovative-patterning complaint placement facilitates the optimal performance and area, which can be subjected to decomposition during production. PrimeTime supports variation impact of multi-valued SPEF model on timing, thanks to innovative patterning.
Custom Designer offers productivity aids like connectivity assisted editing and supports 20-nm constraints, latest local interconnect and cut poly, and correct-by-construction variable size through creation to address design-rule complexity.
Synopsys’ Vice President of Product Marketing, Bijan Kiani stated that the company and TSMC are handling the next-generation requirements of the design community.
Source: http://www.synopsys.com/