Semiconductor Manufacturing International (SMIC) and Synopsys have reported that a wide range of Synopsys DesignWare IP is available for SMIC 40-nm low-leakage (40LL) process technology.
The SMIC 40LL process integrates cutting-edge immersion lithography, ultra low-k dielectric, ultra shallow junction and strain engineering to provide the optimal power and performance needed for consumer and mobile multimedia devices. This broad portfolio of proven IP for SMIC's cutting-edge low-power process allows designers to integrate more capabilities into their sophisticated system-on-chip (SoC) designs with minimal risk and quicker market-reach time.
Since 2005, Synopsys has delivered a broad set of IP for SMIC processes ranging between 130 nm and 40 nm through its partnership with SMIC. Synopsys DesignWare IP that are offered now or slated to be offered later in 2012 for the SMIC 40LL process include
- Interface IP for commonly utilized protocols such as DDR, SATA, MIPI, PCI Express 2.0/1.1, USB 2.0/3.0 and HDMI that lowers interoperability risk
- Logic libraries and embedded memories that allow designers to attain low power and high speed throughout the whole SoC
- Optimized audio codec and data converter IP for a variety of low-power and high-performance applications
SMIC’s Chief Business Officer, Chris Chi stated that the availability of a wide range of silicon-proven IP for high-performance, low-power process technology is essential for firms designing SoCs for use in multimedia consumer applications in China and all over the globe.
Synopsys’ Vice President of Marketing for IP and systems, John Koeter commented that by offering the company’s proven IP for SMIC's 40LL process enables designers to leverage SMIC's cutting-edge low-leakage process technology and incorporate high-quality IP with minimal risk.
Source: http://www.smics.com