Synopsys, Inc. (NASDAQ:SNPS)
, a world leader in software and IP for semiconductor design, verification and
manufacturing, today announced that the Galaxy(TM) Implementation Platform supports
TSMC's 28-nanometer (nm) process technology with Reference Flow 10.0. Galaxy
technologies featured in Reference Flow 10.0 include comprehensive 28-nm design
rule support for place and route, interconnect process modeling and in-design
manufacturing compliance, IEEE 1801-2009 (UPF)-based hierarchical low power
flow support, power-aware design-for-test (DFT), electrical design-for-manufacturing
(eDFM) enhancements and advanced signoff capabilities.
"TSMC and Synopsys have successfully collaborated to deliver 10 generations
of the TSMC Reference Flow," said ST Juang, senior director of Design Infrastructure
Marketing at TSMC. "The combination of Synopsys Galaxy technology and our
28-nanometer process technology in Reference Flow 10.0 provides designers a
solution that addresses manufacturability while balancing the design for optimal
performance and power consumption."
Synopsys' Galaxy Implementation Platform provides support for TSMC 28-nanometer
design rules with IC Compiler place and route, IC Validator physical verification
and Star-RCXT(TM) parasitic extraction. As a key component of Synopsys' Eclypse(TM)
Low Power Solution, the Galaxy Platform includes new hierarchical low power
flow support with IEEE 1801, disjoint voltage area support, new power-aware
technology for Design Compiler DFT synthesis and TetraMAX automatic test pattern
generation (ATPG).
"The enhanced capabilities of our Galaxy Implementation Platform to support
TSMC 28-nm design rules enable the design community to more easily benefit from
TSMC's latest process technology," said Bijan Kiani, vice president of
Product Marketing, Design and Manufacturing Products, at Synopsys. "The
release of Reference Flow 10.0 combines industry-leading EDA solutions from
Synopsys and state-of-the-art manufacturing technology from TSMC to offer designers
a low-risk path from design to silicon for their next-generation products."
Additional Galaxy technologies integrated into Reference Flow 10.0 provide
comprehensive flow support for TSMC's eDFM timing analysis initiative. eDFM
addresses potential parametric performance shifts due to manufacturing process
variation in feature thickness, shape and stress. These technologies include
Seismos stress effect analysis and characterization, PrimeYield CMP modeling
with TSMC's CMP simulator (VCMP), Star-RCXT feature-scale VCMP-aware extraction,
PrimeTime VCMP-aware timing analysis, and PrimeRail VCMP-aware IR/EM analysis.
Posted July 22nd, 2009
