Cadence Design Systems,
Inc. (NASDAQ: CDNS), the leader in global electronic design innovation,
announced today that they have validated a new generation of ASIC libraries
from ARM using the Cadence® Encounter® Digital Implementation System
targeting IBM's 45-nanometer silicon-on-insulator (SOI) manufacturing process.
The development marks another milestone in a multiyear collaboration enabling
efficient utilization of IBM's low-power, high-performance SOI technology for
next-generation designs.
"Our collaboration with Cadence on the early validation of their tools
will ensure design readiness for customers of IBM's 45nm SOI technology. Collectively,
ARM, Cadence and IBM offer a reliable design platform wherever speed, functionality
and low power consumption are needed," said Tom Lantzsch, vice president,
physical IP division, ARM. "These new silicon-validated 45nm SOI libraries
enable the creation of power efficient SOCs, while reducing development time
and cost."
The ARM 45nm SOI libraries were developed using the Cadence Virtuoso® custom
design platform 6.1 and validated on multiple designs in the Cadence Encounter
Digital Implementation System, a complete RTL-to-GDSII design environment that
features the Si2 Common Power Format (CPF) for low power design, native signoff-in-the-loop
for interconnect extraction, timing, power, and signal integrity plus fully
integrated Cadence design-for-manufacturing (DFM) technology. The entire Cadence
end-to-end design, implementation, and verification solution is proven to fully
support the SOI manufacturing process.
"The collaboration among Cadence, ARM and IBM is vital to designers targeting
our SOI technology," said Richard Busch, director, IBM ASIC Products. "It's
imperative that these libraries are designed, verified and implemented in close
correlation to our SOI process so designers can achieve the full benefits of
higher performance and lower power consumption versus bulk CMOS technologies."
"We're excited to play a vital role in this collaboration to deliver advanced
SOI-ready solutions to the design community at a time when the ability to match
performance and power requirements are a growing concern," said Dr. Chi-Ping
Hsu, senior vice president of research and development for the implementation
group at Cadence. "As an industry leader in driving advanced low power
solutions, the collaboration with other leaders in the SOI Consortium enables
rapid deployment of comprehensive high-performance and energy-efficient process
technologies integrated with industry standard design methodologies."
Posted July 27th, 2009
