By Cameron Chai
Synopsys, a global provider of software and IP for design, verification and production of semiconductors, and Shanghai Hua Hong NEC Electronics, a Mainland China developer of IC foundry service, recently declared that the 130nm reference flow, version 3.0 is available.
The development has been made possible by collaboration between the two companies. The system incorporates the Synopsys Eclypse Low Power Solution to the earlier reference flows available to designers who will now be able to access a maximized gateway to HHNEC silicon at 130nm, lowering overall project costs.
The solution combines implementation and verification features of Synopsys' Galaxy Implementation and Discovery Verification platforms to allow for energy efficient methods. Enhanced features include Synopsys’ Formality solution for energy efficient equivalence checking, MVRC to enable static rule checking, Power Compiler for energy optimization, and VCS with MVSIM for simulation over multiple voltages.
The solution was tested using HHNEC’s cell library, SRAM, and IO Library for 130nm. The test chip features a multi-supply and multi-voltage design used for authenticating reference flows.