By Cameron Chai
Fujitsu Semiconductor has standardized design-for-manufacturing (DFM) technologies from Cadence Design Systems for its 28 nm ASIC and system-on-chip (SoC) mixed-signal designs.
The deployment of Cadence’s “in-design” technology would aid Fujitsu in ensuring predictability, high yield and a quicker path for its new chips to attain Silicon Realization. The new generation chips would be a core component of Fujitsu’s sophisticated consumer electronic products.
Cadence’s digital and analog flows designed for Silicon Realization provide DFM in-design technology in Encounter digital and Virtuoso custom/analog flows.
Fujitsu Semiconductor’s System LSI Technology and Design Platform Development Department director, Hiroshi Ikeda, stated that Cadence DFM technologies had been selected after an extensive assessment of various vendors. The DFM technology would help manage the intricacy of its 28 nm effects, with a high quality of silicon and quicker turnaround times, he said. The integration into Cadence Encounter and Virtuoso flows would allow straightforward adoption, he added.
The Cadence Litho Electrical Analyzer, Cadence CMP Predictor and the Cadence Litho Physical Analyzer have been chosen by Fujitsu Semiconductor for its in-design variability optimization and physical signoff for SoC and ASIC designs. The Litho Electrical Analyzer can help identify and optimize libraries for effect variability that is layout-dependent. The Cadence CMP Predictor has the ability to detect through extensive simulations, the topography variations in the manufacturing processes. The Cadence Litho Physical Analyzer enables fast silicon convergence by leveraging foundational algorithms for providing near-linear scalability. These Cadence technologies would enable Fujitsu Semiconductor ensure that its design satisfies the required performance metrics.