CEA-Leti will present six invited papers at the 2015 IEEE International Electron Devices Meeting (IEDM) Dec. 7-9 in Washington, D.C., share the latest results in its new CoolCube program and host a workshop focusing on the Internet of Things on Dec. 6.
In addition, Leti research scientist Sylvain Barraud will receive the 2014 IEEE EDS Paul Rappaport Award for his work in multi-Core/Shell-(SiGe/Si) nanowire transistors. This award recognizes the best scientific paper targeting IEEE transactions on electron devices. The article was selected from more than 600 papers published in 2014.
On Dec. 8, Maud Vinet, Leti’s advanced CMOS manager, will present the latest on Leti’s CoolCube technique for stacking transistors sequentially in the same process flow for 3D-VLSI, at a panel discussion titled, “Is there a potential for a revolution in on-chip interconnect?”
Also on Dec. 8, Carlo Reita, director of nanoelectronics technical marketing and strategy, will participate in a panel discussion on “Emerging Devices – Will they solve the bottlenecks of CMOS?”
The Internet of Things workshop for invited guests at the Churchill Hotel will feature a keynote presentation on “Enabling Next-generation Innovation with 22FDX”, by Subramani Kengeri, vice president of GLOBALFOUNDRIES’ CMOS business unit. The workshop also will focus on energy challenges, new sensor capabilities and enabling applications:
- System challenges for IoT
- Ultra low-power CMOS
- Emerging embedded memories
- Ultra low-power global design
- Sensors for context awareness
- Energy scavenging
- Enabling medicine with IoT
Discussions, networking and cocktails will follow the presentations.
Subjects of the invited papers are:
- Issues for 200mm GaN/Si, from epitaxy to converter topologies
- Implementation of embedded neuromorphic circuits
- Large-area sensing surfaces
- Lensfree microscopy
- Technology scaling and reliability
- New challenges and opportunities for 3D integration
Leti researchers also will join partners to present four papers on vertical resistive RAM for neuromorphic applications, polysilicon nanowire NEMS, a 3D VLSI integration SiCO perspective on low k=4.5 spacer deposited at low temperature and a 3D computational study of van der Waals tunnel transistors.