Cadence Design Systems,
Inc. (NASDAQ: CDNS), the leader in global electronic design innovation,
today announced that its suite of Cadence® Encounter® Digital Implementation
System solutions, including design closure, low-power, DFM, mixed-signal, and
signoff technologies, as well as System-In-Package design technology are included
in TSMC Reference Flow 10.0. The RTL-to-GDSII design capabilities in the Cadence
track enable designers to produce high-yielding, power-efficient designs for
the foundry's most advanced manufacturing processes.
"Reference Flow 10.0 plays a critical role in design enablement for new
process technologies," said S.T. Juang, senior director of Design Infrastructure
Marketing at TSMC. "The close collaboration with Cadence ensures needed
tool enhancements are made ahead of time, as we are entering 28 nanometers."
"Providing best-in-class solutions for today's toughest design challenges
and developing solutions ahead of the curve for tomorrow requires continuous
innovation and tight collaboration with our customers and business partners,"
said Dr. Chi-Ping Hsu, vice president of digital implementation research and
development at Cadence. "Working closely with TSMC helps ensure our leadership
in low-power, mixed-signal, integrated DFM, advanced-node, and signoff technologies,
and enables Cadence to provide a complete and predictable solution from RTL
to final silicon."
DFM, Digital Implementation and Analysis
A key contribution to Reference Flow 10.0 is the industry's first context-aware
electrical analysis of library cell and SOC designs. Using the award-winning
Cadence Litho Electrical Analyzer, designers can electrically fine-tune library
cells and accurately model electrical stress effects, thereby increasing product
quality. In addition, the hierarchical Litho Physical Analyzer produces fast
analysis of the physical manufacturability of nanometer-level devices. Both
of these unique DFM capabilities are integrated into the Encounter Digital Implementation
System, allowing early design stage identification, analysis and repair of potential
Other variation reduction techniques covered under the Cadence track of TSMC
Reference Flow 10.0 include statistical static timing analysis (SSTA), placement
optimization, advanced clock tree analysis and on-chip variation analysis. All
of these techniques are dramatically accelerated through end-to-end support
for multi-processor-based computing platforms.
Building upon the Cadence NanoRoute® Router, which significantly boosts
designer productivity and accelerates overall turnaround time, Cadence delivers
a variety of other DFM techniques, including physical defect analysis, virtual
CMP hot spot analysis, lithography process checking, advanced process modeling,
and substrate noise analysis. All of these capabilities are fully integrated
into the Encounter Digital Implementation System to allow the closest possible
correlation between optimization and signoff.
Advanced Low-Power Design
Cadence introduced its Low-Power Design Solution more than two years ago and
immediately incorporated its features into the TSMC Reference Flow 8.0. Since
then, Cadence has updated its Low-Power Solution with new capabilities, including
hierarchical support for the Si2 Common Power Format (CPF), pulse-latch, and
dual-flop solutions. Because the Cadence Low-Power Solution is also seamlessly
integrated into the Encounter Digital Implementation System, it provides low
cost of ownership and an easy-to-use design environment for low-power design.