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Freescale Semiconductor Successfully Taped Out 45-Nanometer Networking Design

Published on July 28, 2009 at 9:00 AM

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced that Freescale Semiconductor has successfully taped out a 45-nanometer networking design using the Cadence "correct-by-design" prevention, analysis, implementation and signoff solution for faster, more predictable time-to-volume production. The flow incorporates the industry's leading model-based design-for-manufacturing (DFM) prevention, analysis and signoff, including Cadence Litho Physical Analyzer, Cadence CMP Predictor, Cadence Litho Electrical Analyzer, Cadence QRC Extraction, and model-based routing optimization with the Cadence® Encounter® Digital Implementation (EDI) System. This seamless methodology demonstrated significantly faster turnaround time compared to traditional DFM solutions and was used to tape out the design to Chartered Semiconductor Manufacturing.

"For high-volume designs using advanced process nodes, we believe it is a key enabler and differentiator to have silicon-accurate analysis and implementation of yield-critical steps such as lithography and CMP," said Kyle Patterson, manager of DFM Technologies at Freescale Semiconductor. "By incorporating Cadence advanced DFM techniques, both physical and electrical, into implementation, we are able to accurately predict manufacturing issues and prevent them from occurring, and with a methodology that takes a fraction of the time compared to traditional DFM methods. Fundamentally, this allows us to accelerate our time-to-market and time-to-volume requirements."

Through collaborations with leading semiconductor companies such as Freescale, Cadence has developed one of the industry's most complete DFM prevention, analysis and signoff methodologies, enabling design-side optimizations that reduce manufacturing risk. Cadence solutions leverage multi-core distributed processing to seamlessly address increasing design cycle and database size increases at 45- and 32-nanometer process nodes and have proven to deliver near-linear scalability. In addition, Cadence Litho Electrical Analyzer is the industry's first electrical DFM (eDFM) solution in production use at leading semiconductor companies from 90 nanometers down to 40 nanometers, and is currently facilitating 32- and 28-nanometer variability-aware library development.

"Our collective vision is to accurately model manufacturing effects and address them during the design phase," said Dr. Kuang-Kuo "K.K." Lin, senior manager of DFM Services at Chartered. "By working with Cadence to develop silicon-accurate DFM models for analysis and digital implementation, we have produced a DFM flow with distinct benefits for Freescale, which results in faster cycle times."

"The design complexity and stringent manufacturing budgets at 45- and 32-nanometers require early three-way collaboration between the customer, the foundry and EDA, beginning at the library level," said Dave Desharnais, group director of Digital Implementation Solutions at Cadence. "We are pleased that our silicon-proven technology has enabled Freescale's design success and look forward to ensuring their continued design closure successes. Cadence will continue to invest to be a leading provider of the entire manufacturability-aware implementation flow."

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